MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 801

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 14-27
14.5.3.2.13 Transmit Time Stamp Register (TMR_TXTS1–2_H/L)
Transmit stamp register (TMR_TXTSn_H/L). This register holds the value of the TMR_CNT_H/L when
a frame tagged for timestamp capture (via Tx FCB[PTP]) is transmitted. Upon transmission of the start of
frame symbol of such a frame, the value in TMR_CNT_H/L is copied into TMR_TXTSn_H/L.
This register is read only in normal operation.
Offset eTSEC1:0x2_42C0+8 n;
Table 14-28
14.5.3.3
This section describes the control and status registers that are used specifically for receiving Ethernet
frames. All of the registers are 32 bits wide.
Freescale Semiconductor
Reset
16–31
0–15
0–63
Bits
Bits
W
R
eTSEC3:0x2_62C0+8 n
0
TXTS_H/L
TXTS_ID
Name
Name
describes the fields of the TMR_TXTSn_ID register.
describes the fields of the TMR_TXTSn_H/L register.
eTSEC Receive Control and Status Registers
—
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Reserved
Tx time stamp identification field
Time stamp field of the transmitted PTP packet’s start of frame detection.
Table 14-28. TMR_TXTS n _H/L Register Field Descriptions
Table 14-27. TMR_TXTS n _ID Register Field Descriptions
TXTS_H
Figure 14-23. TMR_TXTS n _H/L Register Definition
Figure 14-23
All zeros
31 32
Description
Description
depicts TMR_TXTSn_H/L.
Enhanced Three-Speed Ethernet Controllers
TXTS_L
Access: Read only
14-53
63