MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 334

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DDR Memory Controller
Table 8-49
8.5
The DDR SDRAM controller controls processor and I/O interactions with system memory. It provides
support for JEDEC-compliant DDR3 and DDR2 SDRAMs. The memory system allows a wide range of
memory devices to be mapped to any arbitrary chip select, and support is provided for registered DIMMs
and unbuffered DIMMs. However, registered DIMMs cannot be mixed with unbuffered DIMMs. In
addition, DDR3 DIMM module specifications allow for vendors to use mirrored DIMMs, where some
address and bank address lines are mirrored on the DIMM. The memory controller only supports these if
the DDR_SDRAM_MD_CNTL register is used to initialize memory with DDR_SDRAM_CFG[BI] set.
Figure 8-45
internal mastering device and the address is decoded to generate the physical bank, logical bank, row, and
column addresses. The transaction is compared with values in the row open table to determine if the
address maps to an open page. If the transaction does not map to an open page, an active command is
issued.
The memory interface supports as many as four physical banks of 64-/72-bit wide or 32-/40-bit wide
memory. Bank sizes up to 4 Gbytes are supported, providing up to a maximum of 16 Gbytes of DDR main
memory.
Programmable parameters allow for a variety of memory organizations and timings. Optional error
checking and correcting (ECC) protection is provided for the DDR SDRAM data bus. Using ECC, the
DDR memory controller detects and corrects all single-bit errors within the 64- or 32-bit data bus, detects
all double-bit errors within the 64- or 32-bit data bus, and detects all errors within a nibble. The controller
allows as many as 32 pages to be open simultaneously. The amount of time (in clock cycles) the pages
remain open is programmable with DDR_SDRAM_INTERVAL[BSTOPRE].
8-60
16–23
24–31
8–15
Bits
0–7
Name
SBEC Single-bit error counter. Indicates the number of single-bit errors detected and corrected since the last error
SBET Single-bit error threshold. Establishes the number of single-bit errors that must be detected before an error
Functional Description
—
—
describes the ERR_SBE fields.
is a high-level block diagram of the DDR memory controller. Requests are received from the
Reserved
condition is reported.
Reserved
report. If single-bit error reporting is enabled, an error is reported and a machine check or critical interrupt is
generated when this value equals SBET. SBEC is automatically cleared when the threshold value is reached.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 8-49. ERR_SBE Field Descriptions
Description
Freescale Semiconductor