MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 152

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Signal Descriptions
Note that individual chapters of this document provide details for each signal, describing each signal’s
behavior when the signal is asserted or negated and when the signal is an input or an output.
The following tables provide summaries of signal functions.
function, and
alternate functions, number of signals, and whether the signal is an input, output, or bidirectional. The
direction of the multiplexed signals applies for the primary signal function listed in the left-most column
of the table for that row (and does not apply for the state of the reset configuration signals). Finally, the
table provides a pointer to the table where the signal function is described.
Table 3-1
3-2
MAPAR_ERR
MAPAR_OUT
PCI_AD[31:0]
MDQ[0:63]
MECC[0:7]
MDQS[0:7]
MDQS[0:7]
MCKE[0:3]
MODT[0:3]
MCK[0:5],
MDIC[0:1]
•
•
•
MDM[0:7]
MBA[2:0]
MCS[0:3]
MCK[0:5]
MA[15:0]
MDQS8
MDQS8
MDM8
MRAS
MCAS
Name
MWE
SPI signals
Configuration signals
General-purpose input/output signals
provides a summary of the signals grouped by function.
Table 3-2
DDR data
DDR error correcting code
DDR data mask
DDR ECC data mask
DDR data strobe
DDR ECC data strobe
DDR data strobe (complement)
DDR ECC data strobe
(complement)
DDR bank select
DDR address
DDR write enable
DDR row address strobe
DDR column address strobe
DDR chip select (2/DIMM)
DDR clock enable
DDR differential clocks (3
pairs/DIMM)
DRAM On-Die Termination
Driver impedance calibration
DDR address parity in
DDR address parity out
PCI address/data
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 3-1. MPC8536E Signal Reference by Functional Block
lists the signals alphabetically. These tables detail the signal name, interface,
Description
DDR memory
DDR memory
DDR memory
DDR memory
DDR memory
DDR memory
DDR memory
DDR memory
DDR memory
DDR memory
DDR memory
DDR memory
DDR memory
DDR memory
DDR memory
DDR memory
DDR memory
DDR memory
DDR memory
DDR memory
Functional
Debug/
Block
PCI
Alternate Function(s)
Table 3-1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
lists the signals grouped by
Signals
No. of
64
16
12
32
8
8
1
8
1
8
1
3
1
1
1
4
4
4
2
1
1
Freescale Semiconductor
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
O
I
16-2/16-6
8-3/8-6
8-3/8-6
8-3/8-6
8-3/8-6
8-3/8-6
8-3/8-6
8-3/8-6
8-3/8-6
8-3/8-6
8-3/8-6
8-3/8-6
8-3/8-6
8-3/8-6
8-3/8-6
8-3/8-6
8-3/8-6
8-3/8-6
8-3/8-6
8-3/8-6
8-3/8-6
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