MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 483

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.5.4.2.1
Interrupt sources can be individually enabled by setting the corresponding IER bits (see
the correspondence between IER bits and interrupt sources). If an IER bit is set, the corresponding
interrupt source value is captured in the corresponding interrupt status register (ISR) bit. If an IER bit is
cleared, the corresponding ISR bit remains cleared.
At reset, all IER bits are cleared, so all interrupts are disabled.
10.5.4.2.2
Each ISR bit shows the status of a corresponding interrupt source (see
between ISR bits and interrupt sources). However, if the corresponding IER bit is cleared, then the ISR bit
remains cleared.
ISR bits are cleared either by reset, or by setting the corresponding bits in the ISR or interrupt clear register.
Freescale Semiconductor
36–37,
42–43,
46–47,
50–51,
54–55,
58–59,
16–19,
32–35,
40–41,
44–45,
48–49,
52–53,
56–57,
38-39,
62–63
60–61
Table 10-19. Field Names in Interrupt Enable, Interrupt Status, and Interrupt Clear Registers (continued)
Bits
0–9,
(CRCU,KEU,
PKEU, RNG,
AESU,DEU)
Err and Dn
execution
MDEU,
bits for
AFEU,
Name
units
—
Interrupt Enable Register (IER)
For normal operation the IER should be programmed with the value
0x0031_0fff_0000_0000, which enables all channel interrupts and disables
interrupts from the EUs. The EU interrupt bits are provided as a convenience
during debug: during normal operation, an EU error causes the channel
using that EU to generate the appropriate interrupt to the host.
Interrupt Status Register (ISR)
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Err
0 No error detected.
1 Error detected. Indicates that execution unit status register must be read to determine exact cause
Dn
0 Not Done
1 DONE bit indicates that the corresponding EU has completed its operation. This means that final
Reserved, must be cleared.
of the error.
values are available from EU registers. For EUs with output FIFOs, it means that all text data output
has been placed in the output FIFO. For EUs that provide context out through the output FIFO, the
EU places the context in the output FIFO after asserting PRI_DONE.
NOTE
Description
Table 10-19
for the correspondence
Security Engine (SEC) 3.0
Table 10-19
10-53
for