MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 638

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DUART
A standard UART bus transfer is composed of either three or four parts:
An internal logic sample signal, rxcnt, uses the frequency of the baud-rate generator to drive the bits on
SOUT.
The following sections describe the four components of the serial interface, the baud-rate generator, local
loopback mode, different errors, and FIFO mode.
12.4.1.1
A write to the transmitter holding register (UTHR) generates a START bit on the SOUT signal.
Figure 12-16
new data transfer which is limited to the bit length programmed in the UART line control register
(ULCR).When the bus is idle, SOUT is high.
12.4.1.2
Each data transfer contains 5–8 bits of data. The ULCR data bit length for the transmitter and receiver
UART devices must agree before a transfer begins; otherwise, a parity or framing error may occur. A
transfer begins when UTHR is written. At that time a START bit is generated followed by 5–8 of the data
bits previously written to the UTHR. The data bits are driven from the least significant to the most
significant bits. After the parity and STOP bits, a new data transfer can begin if new data is written to the
UTHR.
12.4.1.3
The user has the option of using even, odd, no parity, or stick parity (see
Registers (ULCRn).”
transfer data. When receiving data a parity error can occur if an unexpected parity value is detected. (See
Section 12.3.1.10, “Line Status Registers
12.4.1.4
The transmitter device ends the write transfer by generating a STOP bit. The STOP bit is always high. The
user can program the length of the STOP bit(s) in the ULCR. Both the receiver and transmitter STOP bit
length must agree before attempting to transfer data. A framing error can occur if an invalid STOP bit is
detected.
12.4.2
Each UART contains an independent programmable baud-rate generator, that is capable of taking the
platform clock input and dividing the input by any divisor from 1 to 2
12-20
•
•
•
•
START bit
Data transfer bits (least-significant bit is first data bit on the bus)
Parity bit (optional)
STOP bits
Baud-Rate Generator Logic
shows that the START bit is defined as a logic 0. The START bit denotes the beginning of a
START Bit
Data Transfer
Parity Bit
STOP Bit
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Both the receiver and transmitter parity definition must agree before attempting to
(ULSRn).”)
16
– 1.
Section 12.3.1.8, “Line Control
Freescale Semiconductor