MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1163

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MPC8536E-ANDROID

Manufacturer Part Number
MPC8536E-ANDROID
Description
HARDWARE/SOFTWARE ANDROID OS
Manufacturer
Freescale Semiconductor
Series
PowerQUICC ™r
Type
MPUr

Specifications of MPC8536E-ANDROID

Contents
Board
For Use With/related Products
MPC8536
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
17.3.8.3.20 PCI Express Bridge Control Register—0x3E
The PCI Express bridge control register is shown in
Table 17-75
Freescale Semiconductor
Offset 0x3E
Reset
15–7
Bits
5–4
W
6
3
2
1
0
R
15
Scnd_RST Secondary bus reset
SERR_EN
VGA_EN
describes the PCI Express bridge control register fields.
ISA_EN
Name
PER
Table 17-75. PCI Express Bridge Control Register Field Description
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Reserved
Reserved
VGA enable
ISA enable
SERR enable. This bit controls the propagation of ERR_COR, ERR_NONFATAL, and ERR_FATAL
responses received on the secondary side.
Parity error response.
Figure 17-77. PCI Express Bridge Control Register
7
Scnd_RST
All zeros
Figure
6
Description
17-77.
5
4
VGA_EN ISA_EN SERR_EN
3
PCI Express Interface Controller
2
Access: Read/Write
1
PER
17-67
0

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