MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1302

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Secure Digital Host Controller
20-28
CTOESEN
CINTSEN
BWRSEN
DINTSEN
CRMSEN
BRRSEN
BGESEN
CINSEN
CCSEN
TCSEN
16–22
Field
15
23
24
25
26
27
28
29
30
31
The eSDHC may sample the card interrupt signal during the interrupt period
and hold its value in the flip-flop. As a result of synchronization, there is a
delay in the card interrupt (which is asserted from the card) to the time the
host system is informed.
To detect a SDHC_CMD line conflict, the host driver must set both
CTOESEN and CCESEN bits.
Command timeout error status enable
0 Masked
1 Enabled
Reserved
Card interrupt status enable. If this bit is cleared, the eSDHC clears the interrupt request to the system. The
card interrupt detection is stopped when this bit is cleared and restarted when this bit is set. To prevent
inadvertent interrupts, the host driver should clear this bit before servicing the card interrupt and should set
this bit again after all interrupt requests from the card are cleared.
0 Masked
1 Enabled
Card removal status enable
0 Masked
1 Enabled
Card insertion status enable
0 Masked
1 Enabled
Buffer read ready status enable
0 Masked
1 Enabled
Buffer write ready status enable
0 Masked
1 Enabled
DMA interrupt status enable
0 Masked
1 Enabled
Block gap event status enable
0 Masked
1 Enabled
Transfer complete status enable
0 Masked
1 Enabled
Command complete status enable
0 Masked
1 Enabled
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 20-18. IRQSTATEN Field Descriptions (continued)
NOTE
Description
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