MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 532

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Security Engine (SEC) 3.0
10.7.3.8
The CRCU interrupt status register indicates which unmasked errors have occurred and have generated
error interrupts to the channel. Each bit in this register can only be set if the corresponding bit of the CRCU
interrupt mask register is zero (see
interrupt mask register bit is set, the corresponding CRCU interrupt status bit is always zero regardless of
the error status.
If the CRCU interrupt status register is non-zero, then the CRCU halts and the CRCU error interrupt signal
is asserted to the controller (see
CRCU is being operated in channel-driven mode, then an interrupt signal is generated to the channel to
which this EU is assigned. The EU error then appears in bit 55 of the channel status register (see
Table
10-102
48–55
56–57
59–60
0–47
Bits
10-15) and generates a channel error interrupt to the controller.
58
61
62
63
CRCU Interrupt Status Register
Field Name
HALT
ICCR
IFL
RD
—
—
EI
DI
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Reserved
Input FIFO Level: The number of dwords currently in the input FIFO
Reserved
Indicates when the CRCU core has halted due to an error.
0 CRCU not halted
1 CRCU core halted (Must be reset/re-initialized)
Note: Because the error causing the CRCU to stop operating may be masked to the
Integrity Check Comparison Result
00 No integrity check comparison was performed.
01 The integrity check comparison passed.
10 The integrity check comparison failed.
11 Reserved
Note: A passed or failed result is generated only if ICV checking is enabled and the
Error interrupt.Reflects the state of the error interrupt signal, as sampled by the controller
interrupt status register
0 CRCU is not signaling error
1 CRCU is signaling error
Done Interrupt: Reflects the state of the done interrupt signal, as sampled by the controller
interrupt status register
0 Processing not done
1 All bytes processed
Reset Done: Indicates when the CRCU has completed its reset sequence, as reflected in
the signal sampled by the appropriate channel.
0 Reset in progress
1 Reset done
Table 10-43. CRCU Status Register Bit Definitions
interrupt status register, the status register is used to provide a second source of
information regarding errors preventing normal operation.
algorithm selected is f9.
Section 10.5.4.2.2, “Interrupt Status Register
Section 10.7.3.9, “CRCU Interrupt Mask
(Section 10.5.4.2.2, “Interrupt Status Register
(Section 10.5.4.2.2, “Interrupt Status Register
Description
Register”). If a CRCU
(ISR)”). In addition, if the
Freescale Semiconductor
(ISR)”).
(ISR)”).