MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1366

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Universal Serial Bus Interfaces
21.3.2.18 Endpoint Flush Register (ENDPTFLUSH)—Non-EHCI
This register is not defined in the EHCI specification. This register is only used in device mode.
21.3.2.19 Endpoint Status Register (ENDPTSTATUS)—Non-EHCI
This register is not defined in the EHCI specification. This register is only used in device mode.
21-32
Offset 0x1B4
Offset 0x1B8
Reset
Reset
31–22
21–16 FETB Flush endpoint transmit buffer. Writing a one to a bit(s) in this register will cause the associated endpoint(s) to
31–22
21–16 ETBR Endpoint transmit buffer ready. One bit for each endpoint indicates status of the respective endpoint buffer.
15–6
Bits
5–0
Bits
W
W
R
R
31
31
Name
FERB Flush endpoint receive buffer. Writing a one to a bit(s) will cause the associated endpoint(s) to clear any primed
Name
—
—
—
Reserved, should be cleared.
clear any primed buffers. If a packet is in progress for one of the associated endpoints, then that transfer will
continue until completion. Hardware will clear this register after the endpoint flush operation is successful.
FETB[5] (bit 21 of the register) corresponds to endpoint 5.
Reserved, should be cleared.
buffers. If a packet is in progress for one of the associated endpoints, then that transfer will continue until
completion. Hardware will clear this register after the endpoint flush operation is successful. FERB[5]
corresponds to endpoint 5.
Reserved, should be cleared
This bit is set by the hardware as a response to receiving a command from a corresponding bit in the
ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and
endpoint indicating ready. This delay time varies based upon the current USB traffic and the number of bits
set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through
the ENDPTFLUSH register. ETBR[5] (bit 21 of the register) corresponds to endpoint 5.
Note that these bits will be momentarily cleared by hardware during hardware endpoint re-priming operations
when a dTD is retired, and the dQH is updated.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
—
—
Table 21-27. ENDPTSTATUS Register Field Descriptions
Table 21-26. ENDPTFLUSH Register Field Descriptions
Figure 21-25. Endpoint Status (ENDPTSTATUS)
Figure 21-24. Endpoint Flush (ENDPTFLUSH)
22 21
22
ETBR
FETB
19
16 15
16 15
All zeros
All zeros
Description
Description
—
—
6
6
Freescale Semiconductor
5
5
Access: Read/Write
Access: Read only
ERBR
FERB
0
0