MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 183

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.4.3.3
The DDR PLL inputs, shown in
DDR complex clock. The DDR complex clock drives the DDR data rate, which is 2 times the rate at which
commands are issued on the DDR interface.
This DDR complex clock domain is asynchronous to the platform clock or CCB clock domain, and is
sourced from a separate PLL than the rest of the platform, unless the DDR PLL encoding for synchronous
mode operation is selected. When synchronous mode is selected, the DDR complex is driven by the CCB
clock, which becomes the DDR data rate.
There is no default value for this PLL ratio; these signals must be pulled to the desired values. Note that
the encoded values latched on these signals during POR—and not the actual values on the pins—are
accessible in the PORPLLSR (POR PLL status register), as described in
Status Register
4.4.3.4
The SYSCLK speed configuration inputs, shown in
operation with the SYSCLK clock frequencies in use. The default setting is appropriate for SYSCLK
operating above 66 MHz; for low speed operation (SYSCLK at or below 66 MHz) this POR configuration
input should be low during HRESET. If this configuration is not set properly, behavior of the system may
be unreliable. Note that the value latched on this signal during POR is accessible through the
memory-mapped PORDEVSR, described
(PORDEVSR).”
Freescale Semiconductor
TSEC_1588_TRIG_OUT[0:1],
LGPL1/LFALE
Functional
Default (1)
TSEC_1588_CLK_OUT
Signal
Functional Signals
No Default
DDR PLL Ratio Configuration
System Speed Configuration
(PORPLLSR).”
Reset Configuration
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
cfg_sys_speed
Name
Reset Configuration Name Value (Binary) DDR Complex Clock: DDR Clock Ratio
Table 4-11. DDR Complex Clock PLL Ratios
Table
Table 4-12. System Speed Configuration
cfg_ddr_pll[0:2]
(Binary)
4-11, establish the clock ratio between the DDRCLK input and the
Value
0
1
inSection 23.4.1.4, “POR Device Status Register
SYSCLK frequency at or below 66 MHz
SYSCLK frequency above 66 MHz
Table 4-12
000
001
010
011
100
101
110
111
configure internal logic for proper
Meaning
Section 23.4.1.1, “POR PLL
Synchronous mode
Reset, Clocking, and Initialization
Reserved
10:1
12:1
3:1
4:1
6:1
8:1
4-13