MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1293

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

There are three ways to restart the transfer after a stop at the block gap. The appropriate method depends
on whether the eSDHC issues a suspend command or the SD card accepts the suspend command:
Any time PROCTL[SABGREQ] stops the data transfer, the host driver should wait for IRQSTAT[TC]
before attempting to restart the transfer. When restarting the data transfer by continue request, the host
driver should clear PROCTL[SABGREQ] before or simultaneously.
20.4.9
The system control register is shown in
Freescale Semiconductor
Offset: 0x02C (SYSCTL)
Reset
Reset
D3CD
29–30
•
•
•
Field
DTW
28
31
W
W
R
R
If the host driver does not issue a suspend command, the continue request should be used to restart
the transfer.
If the host driver issues a suspend command and the SD card accepts it, a resume command should
be used to restart the transfer.
If the host driver issues a suspend command and the SD card does not accept it, PROCTL[CREQ]
should be used to restart the transfer.
16
0
1
0
System Control Register (SYSCTL)
SDHC_DAT3 as card detection pin. If this bit is set, SDHC_DAT3 should be pulled down to act as a card detection
pin. Be cautious when using this feature, because SDHC_DAT3 is chip-select for SPI mode, and a pull-down on
this pin and CMD0 may set the card into SPI mode, which the eSDHC does not support.
0 SDHC_DAT3 does not monitor card insertion
1 SDHC_DAT3 is card detection pin
Data transfer width. Selects the data width of the SD bus. The host driver should set it to match the data width
of the card.
00 1-bit mode
01 4-bit mode
10 8-bit mode
11 Reserved
Reserved
0
0
—
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
0
0
Table 20-12. PROCTL Field Descriptions (continued)
SDCLKFS
0
0
3
Figure 20-11. System Control Register (SYSCTL)
INITA
0
0
4
RSTD RSTC RSTA
5
0
0
Figure
0
0
6
20-11.
23
0
0
7
Description
24
0
0
8
0
0
DVS
—
0
0
11
27
Enhanced Secure Digital Host Controller
0
0
—
12
28
0
0
PEREN HCKEN IPGEN
29
0
0
DTOCV
Access: Mixed
30
0
0
20-19
15
31
0
0