MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 498

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Security Engine (SEC) 3.0
10.7.1.10 AESU End of Message Register
The AESU end of message register, shown in
message block has been written to the input FIFO (in channel-driven access, this signaling is done
automatically). The AESU will not process the last block of data in its input FIFO until this register is
written. Once the end of message register is written, the AESU processes any remaining data in the input
FIFO and generates the done interrupt.
The value written to this register does not matter: ordinarily, zero is written. A read of this register always
returns a zero value.
10.7.1.11 AESU Context Registers
There are twelve 64-bit context data registers that allow the host to read/write the contents of the context
used to process a message. The context must be written prior to the key data. If the context registers are
written during message processing, a context error is generated. All context registers are cleared when an
initialization or a hard or soft reset is performed.
If a message is processed through the AESU in two separate operations (that is, using two descriptors),
then the context must be read from the SEC at the end of the first operation and then restored at the
beginning of the second operation.
Context is always read and restored as a contiguous subset of the twelve context registers ending with the
highest numbered register used in that cipher mode. For example, when restoring context in CTR cipher
mode (which uses context registers 5–7, as shown in
(where registers 1–4 must be filled with zeros).
Context register assignments for cipher modes for confidentiality, data integrity, and combined
confidentiality and integrity are described in the following subsections.
10.7.1.11.1 Context for Confidentiality Cipher Modes
The context registers for the different cipher modes which provide confidentiality only are summarized in
Table
10-68
Offset 0x3_4050
Reset
W
R
10-29. The registers are described in more detail in the following subsections.
0
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Figure 10-29. AESU End of Message Register
Figure
AESU End of Message
All zeros
10-29, is used to signal to the AESU that the final
Table
10-29), context registers 1–7 must be written
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Access:Write only
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