MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 69

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure
Number
15-5
15-6
15-7
15-8
15-9
15-10
15-11
15-12
15-13
15-14
15-15
15-16
15-17
15-18
15-19
15-20
15-21
15-22
15-23
15-24
15-25
15-26
15-27
15-28
16-1
16-2
16-3
16-4
16-5
16-6
16-7
16-8
16-9
16-10
16-11
16-12
16-13
16-14
16-15
16-16
16-17
Freescale Semiconductor
Status Registers (SRn)......................................................................................................... 15-11
Basic Chaining Mode Flow Chart....................................................................................... 15-13
Extended Current Link Descriptor Address Registers (ECLNDARn) ............................... 15-14
Current Link Descriptor Address Registers (CLNDARn) .................................................. 15-14
Source Attributes Registers (SATRn) ................................................................................. 15-15
Source Address Registers (SARn) ...................................................................................... 15-16
Destination Attributes Registers (DATRn) ......................................................................... 15-16
Destination Address Registers (DARn) .............................................................................. 15-17
Byte Count Registers (BCRn)............................................................................................. 15-18
Next Link Descriptor Address Registers (NLNDARn) ...................................................... 15-18
Extended Next Link Descriptor Address Registers (ENLNDARn).................................... 15-19
Extended Current List Descriptor Address Registers (ECLSDARn) ................................. 15-20
Current List Descriptor Address Registers (CLSDARn) .................................................... 15-20
Extended Next List Descriptor Address Registers (ENLSDARn)...................................... 15-21
Next List Descriptor Address Registers (NLSDARn) ........................................................ 15-21
Source Stride Registers (SSRn) .......................................................................................... 15-22
Destination Stride Registers (DSRn) .................................................................................. 15-22
DMA General Status Register (DGSR) .............................................................................. 15-23
External Control Interface Timing ...................................................................................... 15-30
Stride Size and Stride Distance ........................................................................................... 15-32
DMA Transaction Flow with DMA Descriptors ................................................................ 15-35
List Descriptor Format ........................................................................................................ 15-36
Link Descriptor Format....................................................................................................... 15-36
DMA Data Paths ................................................................................................................. 15-38
PCI Controller Block Diagram ............................................................................................. 16-2
PCI Interface External Signals.............................................................................................. 16-6
PCI CFG_ADDR Register .................................................................................................. 16-14
PCI CFG_DATA Register ................................................................................................... 16-15
PCI INT_ACK Register ...................................................................................................... 16-15
PCI Outbound Translation Address Registers (POTARn) .................................................. 16-16
PCI Outbound Translation Extended Address Registers (POTEARn) ............................... 16-16
PCI Outbound Window Base Address Registers (POWBARn) ......................................... 16-17
PCI Outbound Window 0 (Default) Attributes Register (POWAR0) ................................. 16-18
PCI Outbound Window 1–4 Attributes Registers (POWAR1–POWAR4) ......................... 16-18
PCI Inbound Translation Address Registers (PITARn) ...................................................... 16-20
PCI Inbound Window Base Address Registers................................................................... 16-20
PCI Inbound Window Base Extended Address Registers (PIWBEARn) ........................... 16-21
PCI Inbound Window Attributes Registers......................................................................... 16-21
PCI Error Detect Register (ERR_DR) ................................................................................ 16-24
PCI Error Capture Disable Register (ERR_CAP_DR) ....................................................... 16-25
PCI Error Enable Register (ERR_EN)................................................................................ 16-26
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
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