MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 616

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

I
11.5.7.2
When a master loses arbitration the following conditions all occur:
Thus, the slave interrupt service routine should first test I2CSR[MAL] and software should clear it if it is
set. See
11.5.8
Figure 11-11
flowchart may result in unpredictable I
service routine may need to set I2CCR[TXAK] when the next-to-last byte is to be accepted. It is
recommended that an msync instruction follow each I
instruction execution.
11-24
2
C Interfaces
•
•
•
I2CSR[MAL] is set
I2CCR[MSTA] is cleared (changing the master to slave mode)
An interrupt occurs (if enabled) at the falling edge of the 9th clock of this transfer
Section 11.4.2.1, “Arbitration Control,”
Interrupt Service Routine Flowchart
shows an example algorithm for an I
Loss of Arbitration and Forcing of Slave Mode
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
2
C bus behavior. However, in the slave receive mode the interrupt
for more information.
2
C interrupt service routine. Deviation from the
2
C register read or write to guarantee in-order
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