MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 906
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MPC8536E-ANDROID
Manufacturer Part Number
MPC8536E-ANDROID
Description
HARDWARE/SOFTWARE ANDROID OS
Manufacturer
Freescale Semiconductor
Series
PowerQUICC ™r
Type
MPUr
Datasheets
1.MPC8536EBVTAVLA.pdf
(127 pages)
2.MPC8536EBVTAVLA.pdf
(2 pages)
3.MPC8536EBVTAVLA.pdf
(1706 pages)
Specifications of MPC8536E-ANDROID
Contents
Board
For Use With/related Products
MPC8536
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Enhanced Three-Speed Ethernet Controllers
14.6.2.3
Figure 14-138
using the 8-bit FIFO interface.
The 8-bit FIFO interface has 25 signals (including the flow control signals). Illustrative timing of the
GMII-style FIFO mode is shown in
14-158
1
The flow control signals (TSEC n _CRS and TSEC n _COL) are common to all of the FIFO modes.
8-Bit GMII-Style Packet FIFO Mode
TSEC n _CRS becomes an output signal in FIFO modes only.
depicts the signals required to establish eTSEC module connection with an external device
TX_ER/RX_ER
TX_EN/RX_DV
eTSEC
TXD/RXD[7:0]
TX/RX_CLK n
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Figure 14-139. 8-Bit GMII-Style Packet FIFO Timing
Figure 14-138. eTSEC-FIFO (8-Bit) Connection
Reflected Transmit Clock (TSEC n _GTX_CLK)
Figure
Transmit Flow Control
Receive Flow Control
Receive Data Valid (TSEC n _RX_DV)
Transmit Data (TSEC
Transmit Enable (TSEC n _TX_EN)
Transmit Clock (TSEC n _TX_CLK)
Receive Data (TSEC
Receive Clock (TSEC n _RX_CLK)
SOP
Transmit Error (TSEC n _TX_ER)
Receive Error (TSEC n _RX_ER)
14-139.
1
1
n
n
(TSEC n _CRS)
(TSEC n _COL)
_TXD[7:0])
_RXD[7:0])
EOP
with 8-Bit
Interface
ASIC
FIFO
Freescale Semiconductor
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