MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 376

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Programmable Interrupt Controller (PIC)
9.1.4.1
When an interrupt request is delivered to the PIC, the corresponding interrupt destination register is
checked to determine where the request should be routed, as follows:
9.1.4.2
Following its reset (by default), the PIC directs all timer, shared message signaled, and interrupts from
external and internal sources to int output (connected to the int signal of the processor core).
All other interrupts have more destination options, but only one destination can be chosen for a single
interrupt. Instead of being routed to int, these interrupts can be routed to the core through IRQ_OUT or
cint. These options are selected by writing to the EP or CI fields in the appropriate destination register.
9.1.4.3
Table 9-2
that control them. Only the internal interrupts used are listed; that is, the numbers are not consecutive.
9-6
•
•
•
•
•
•
Interprocessor interrupts (IPI)—Intended for communication between different processor cores on
the same device. (Can be used for self-interrupt in single-core implementations.)
Message registers—From within the PIC. Triggered on register write, cleared on read. Used for
interprocessor communication.
Shared message signaled registers—From within the PIC. Triggered on register write, cleared on
read. Used for cross-program communication.
If xIDRn[EP] = 1 (and all other destination bits are zero), the interrupt is routed off-chip to the
external IRQ_OUT signal. Or if the PCI Express controller is in EP mode and automatically
generates a PCI Express MSI transaction. See
If xIDR[CI] is set (and all other destination bits are zero), the interrupt is routed to cint. .
If xIDRn[P0] is set (and all other destination bits are zero) the interrupt is routed to int0. Setting
xIDRn[P1] likewise routs the interrupt to int1 In this case, the interrupt is latched by the interrupt
pending register (IPR) and the interrupt flow is as described in
Control.”
shows the assignments of the internal interrupt sources and how they are mapped to the registers
Internal Interrupt Number
Interrupt Routing—Mixed Mode
Interrupt Destinations
Internal Interrupt Sources
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
0
1
2
3
4
5
6
7
Table 9-2. Internal Interrupt Assignments
L2 cache
ECM
DDR DRAM controller
eLBC controller
DMA 1 channel 1
DMA 1 channel 2
DMA 1 channel 3
DMA 1 channel 4
Section 17.4.2.1.2, “Hardware MSI
Interrupt Source
Section 9.4.1, “Flow of Interrupt
Freescale Semiconductor
Generation.”