MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 364
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MPC8536E-ANDROID
Manufacturer Part Number
MPC8536E-ANDROID
Description
HARDWARE/SOFTWARE ANDROID OS
Manufacturer
Freescale Semiconductor
Series
PowerQUICC ™r
Type
MPUr
Datasheets
1.MPC8536EBVTAVLA.pdf
(127 pages)
2.MPC8536EBVTAVLA.pdf
(2 pages)
3.MPC8536EBVTAVLA.pdf
(1706 pages)
Specifications of MPC8536E-ANDROID
Contents
Board
For Use With/related Products
MPC8536
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- Current page: 364 of 1706
- Download datasheet (15Mb)
DDR Memory Controller
8-90
ODT_WR_CFG
ODT_PD_EXIT
ODT_RD_CFG
PRETOACT
ACTTOPRE
ACTTORW
Parameter
CASLAT
Table 8-69. Programming Differences Between Memory Types (continued)
Chip Select ODT Read
Configuration
Chip Select ODT Write
Configuration
ODT Powerdown Exit
Precharge to Activate
Timing
Activate to Precharge
Timing
Activate to Read/Write
Timing
CAS Latency
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Description
DDR2
DDR3
DDR2
DDR3
DDR3
DDR2
DDR3
DDR2
DDR3
DDR2
DDR3
DDR3
DDR2
DDR2
could be set differently depending on system
topology. However, systems with only 1 chip select
will typically not use ODT when issuing reads to
the memory.
could be set differently depending on system
topology. However, systems with only 1 chip select
typically do not use ODT when issuing reads to
the memory.
could be set differently depending on system
topology. However, ODT will typically be set to
assert for the chip select that is getting written to
(value would be set to 001).
could be set differently depending on system
topology. However, ODT typically is set to assert
for the chip select that is getting written to (value
would be set to 001).
specifications for the memory used. The JEDEC
parameter this applies to is t
Should be set to 0001 for DDR3. The powerdown
times (t
controlled via TIMING_CFG_0[ACT_PD_EXIT]
and TIMING_CFG_0[PRE_PD_EXIT].
the memory used (t
the memory used (t
Should be set, along with the Extended Activate to
Precharge Timing, according to the specifications
for the memory used (t
Should be set, along with the Extended Activate to
Precharge Timing, according to the specifications
for the memory used (t
the memory used (t
the memory used (t
Latency, to the desired CAS latency
Should be set, along with the Extended CAS
Latency, to the desired CAS latency
Can be enabled to assert ODT if desired. This
Can be enabled to assert ODT if desired. This
Can be enabled to assert ODT if desired. This
Can be enabled to assert ODT if desired. This
Should be set according to the DDR2
Should be set according to the specifications for
Should be set according to the specifications for
Should be set according to the specifications for
Should be set according to the specifications for
Should be set, along with the Extended CAS
XP
and t
Differences
XPDLL
RP
RP
RCD
RCD
) required for DDR3 are
)
)
RAS
RAS
)
)
)
)
AXPD
.
Freescale Semiconductor
Section/page
8.4.1.2/8-13
8.4.1.2/8-13
8.4.1.5/8-17
8.4.1.6/8-19
8.4.1.6/8-19
8.4.1.6/8-19
8.4.1.6/8-19
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