MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1531

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MPC8536E-ANDROID

Manufacturer Part Number
MPC8536E-ANDROID
Description
HARDWARE/SOFTWARE ANDROID OS
Manufacturer
Freescale Semiconductor
Series
PowerQUICC ™r
Type
MPUr

Specifications of MPC8536E-ANDROID

Contents
Board
For Use With/related Products
MPC8536
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
23.4.1.30 SerDes2 Control Register 0 (SRDS2CR0)
Shown in
Freescale Semiconductor
Offset 0xE_3100
Reset
Reset
19–31
W
W
Bits
R
R
15
16
17
18
16
0
0
0
Figure
PPSEN
17
Name
X3SG
X3SH
X3SF
0
1
1
23-30, the SRDS2CR0 contains the functional control bits for the SerDes2 logic.
TXEQA
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
0
0
2
Table 23-32. SRDS1CR2 Field Descriptions (continued)
Figure 23-30. SerDes2 Control Register 0 (SRDS2CR0)
0 Normal
1 The transmitter ouput is disabled and place in a three-state condition
Recommended setting per protocol:
PCI-Express: 0
0 Normal
1 The transmitter ouput is disabled and place in a three-state condition
Recommended setting per protocol:
PCI-Express: 0
0 Normal
1 The transmitter ouput is disabled and place in a three-state condition
Recommended setting per protocol:
PCI-Express: 0
0 Pin power saving disabled
1 Pin power saving enabled (recommended)
Reserved
Lane F transmitter three-state
Lane G transmitter three-state
Lane H transmitter three-state
Pin power save enable
19
1
0
3
20
4
0
0
21
0
1
5
TXEQE
0
0
6
23
1
0
7
SDPD
24
0
0
8
Description
25
0
0
26
0
1
11
27
0
1
12
28
0
0
Access: Read/Write
13
0
0
Global Utilities
14
0
0
23-39
15
31
0
0

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