MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 589

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 10-74
10.7.8.6
The RNGU interrupt mask register controls the result of detected errors. For a given error (as defined in
Section 10.7.8.5, “RNGU Interrupt Status
the error is disabled; no error interrupt occurs and the interrupt status register is not updated to reflect the
error. If the corresponding bit is not set, then upon detection of an error, the interrupt status register is
updated to reflect the error, causing assertion of the error interrupt signal, and causing the module to halt
processing.
The bit fields of the RNGU interrupt mask register are shown in
Freescale Semiconductor
Offset 0x3_A030
Reset
W
R
52–55
58–61
0–50
Bits
0
51
56
57
62
63
describes the RNGU interrupt status register fields.
RNGU Interrupt Mask Register
Name
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
OFU
ME
—
IE
—
AE
—
—
Table 10-74. RNGU Interrupt Status Register Field Descriptions
Figure 10-107. RNGU Interrupt Status Register
Reserved
Internal Error
0 No internal error detected
1 Internal error
Reserved
Mode Error. Indicates that the host has attempted to write an illegal value to the
mode register
0 Valid data
1 Invalid data error
Address Error. An illegal read or write address was detected within the RNGU
address space.
0 No error detected
1 Address error
Reserved
Output FIFO Underflow. The RNGU Output FIFO was read while empty.
0 No overflow detected
1 Output FIFO has underflowed
Reserved
—
Register”), if the corresponding bit in this register is set, then
All zeros
Description
Figure
10-108.
50 51 52
IE
—
55 56
ME AE
Security Engine (SEC) 3.0
Access: Read/Write
57 58
—
61
OFU —
62
10-159
63