MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 28

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Paragraph
Number
14.6.2.4
14.6.2.5
14.6.3
14.6.3.1
14.6.3.1.1
14.6.3.1.2
14.6.3.2
14.6.3.3
14.6.3.4
14.6.3.5
14.6.3.5.1
14.6.3.5.2
14.6.3.6
14.6.3.7
14.6.3.7.1
14.6.3.7.2
14.6.3.8
14.6.3.9
14.6.3.10
14.6.3.10.1
14.6.3.10.2
14.6.3.10.3
14.6.3.11
14.6.3.12
14.6.3.13
14.6.4
14.6.4.1
14.6.4.2
14.6.4.3
14.6.5
14.6.5.1
14.6.5.2
14.6.5.2.1
14.6.5.2.2
14.6.5.2.3
14.6.5.2.4
14.6.5.2.5
14.6.5.2.6
14.6.5.2.7
14.6.5.2.8
14.6.5.3
xxviii
Gigabit Ethernet Controller Channel Operation .................................................... 14-160
TCP/IP Off-Load ................................................................................................... 14-176
Quality of Service (QoS) Provision ....................................................................... 14-181
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
8-Bit Encoded Packet FIFO Mode .................................................................... 14-159
FIFO Interface Signal Summary........................................................................ 14-159
Initialization Sequence....................................................................................... 14-160
Soft Reset and Reconfiguring Procedure........................................................... 14-161
Gigabit Ethernet Frame Transmission ............................................................... 14-162
Gigabit Ethernet Frame Reception .................................................................... 14-163
Ethernet Preamble Customization ..................................................................... 14-164
RMON Support.................................................................................................. 14-166
Frame Recognition............................................................................................. 14-166
Magic Packet Mode ........................................................................................... 14-170
Flow Control...................................................................................................... 14-170
Interrupt Handling ............................................................................................. 14-171
Inter-Frame Gap Time ....................................................................................... 14-174
Internal and External Loop Back ....................................................................... 14-175
Error-Handling Procedure.................................................................................. 14-175
Frame Control Blocks........................................................................................ 14-177
Transmit Path Off-Load and Tx PTP Packet Parsing ........................................ 14-178
Receive Path Off-Load ...................................................................................... 14-179
Receive Parser ................................................................................................... 14-181
Receive Queue Filer .......................................................................................... 14-183
Transmission Scheduling................................................................................... 14-189
Hardware Controlled Initialization ................................................................ 14-160
User Initialization .......................................................................................... 14-160
User-Defined Preamble Transmission ........................................................... 14-165
User-Visible Preamble Reception.................................................................. 14-165
Destination Address Recognition and Frame Filtering ................................. 14-167
Hash Table Algorithm.................................................................................... 14-168
Interrupt Coalescing ...................................................................................... 14-172
Interrupt Coalescing By Frame Count Threshold.......................................... 14-172
Interrupt Coalescing By Timer Threshold ..................................................... 14-173
Filing Rules ................................................................................................... 14-184
Comparing Properties with Bit Masks........................................................... 14-185
Special-Case Rules ........................................................................................ 14-186
Filer Interrupt Events..................................................................................... 14-186
Setting Up the Receive Queue Filer Table .................................................... 14-187
Filer Example—802.1p Priority Filing.......................................................... 14-187
Filer Example—IP Diff-Serv Code Points Filing.......................................... 14-188
Filer Example—TCP and UDP Port Filing .................................................. 14-188
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