MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 24

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Paragraph
Number
14.5.3.2
14.5.3.2.1
14.5.3.2.2
14.5.3.2.3
14.5.3.2.4
14.5.3.2.5
14.5.3.2.6
14.5.3.2.7
14.5.3.2.8
14.5.3.2.9
14.5.3.2.10
14.5.3.2.11
14.5.3.2.12
14.5.3.2.13
14.5.3.3
14.5.3.3.1
14.5.3.3.2
14.5.3.3.3
14.5.3.3.4
14.5.3.3.5
14.5.3.3.6
14.5.3.3.7
14.5.3.3.8
14.5.3.3.9
14.5.3.3.10
14.5.3.3.11
14.5.3.3.12
14.5.3.3.13
14.5.3.3.14
14.5.3.4
14.5.3.4.1
14.5.3.4.2
14.5.3.4.3
14.5.3.4.4
14.5.3.4.5
14.5.3.5
14.5.3.5.1
14.5.3.5.2
14.5.3.5.3
14.5.3.5.4
14.5.3.5.5
xxiv
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
eTSEC Transmit Control and Status Registers.................................................... 14-40
eTSEC Receive Control and Status Registers ..................................................... 14-53
MAC Functionality.............................................................................................. 14-71
MAC Registers .................................................................................................... 14-74
Transmit Control Register (TCTRL) ............................................................... 14-40
Transmit Status Register (TSTAT)................................................................... 14-42
Default VLAN Control Word Register (DFVLAN) ........................................ 14-46
Transmit Interrupt Coalescing Register (TXIC).............................................. 14-47
Transmit Queue Control Register (TQUEUE) ................................................ 14-48
TxBD Ring 0–3 Weighting Register (TR03WT)............................................. 14-49
TxBD Ring 4–7 Weighting Register (TR47WT)............................................. 14-49
Transmit Data Buffer Pointer High Register (TBDBPH)................................ 14-50
Transmit Buffer Descriptor Pointers 0–7 (TBPTR0–TBPTR7) ...................... 14-50
Transmit Descriptor Base Address High Register (TBASEH)........................ 14-51
Transmit Descriptor Base Address Registers (TBASE0–TBASE7) ............... 14-52
Transmit Time Stamp Identification Register (TMR_TXTS1–2_ID) ............. 14-52
Transmit Time Stamp Register (TMR_TXTS1–2_H/L) ................................. 14-53
Receive Control Register (RCTRL) ................................................................ 14-54
Receive Status Register (RSTAT).................................................................... 14-56
Receive Interrupt Coalescing Register (RXIC) ............................................... 14-59
Receive Queue Control Register (RQUEUE) ................................................. 14-60
Receive Bit Field Extract Control Register (RBIFX)...................................... 14-61
Receive Queue Filer Table Address Register (RQFAR) ................................. 14-63
Receive Queue Filer Table Control Register (RQFCR) .................................. 14-63
Receive Queue Filer Table Property Register (RQFPR) ................................. 14-65
Maximum Receive Buffer Length Register (MRBLR) ................................... 14-68
Receive Data Buffer Pointer High Register (RBDBPH) ................................. 14-68
Receive Buffer Descriptor Pointers 0–7 (RBPTR0–RBPTR7) ....................... 14-69
Receive Descriptor Base Address High Register (RBASEH)......................... 14-70
Receive Descriptor Base Address Registers (RBASE0–RBASE7) ................ 14-70
Receive Stamp Register (TMR_RXTS_H/L).................................................. 14-71
Configuring the MAC ..................................................................................... 14-71
Controlling CSMA/CD.................................................................................... 14-71
Handling Packet Collisions ............................................................................ 14-72
Controlling Packet Flow.................................................................................. 14-72
Controlling PHY Links.................................................................................... 14-73
MAC Configuration 1 Register (MACCFG1)................................................. 14-74
MAC Configuration 2 Register (MACCFG2)................................................. 14-76
Inter-Packet Gap/Inter-Frame Gap Register (IPGIFG) ................................... 14-78
Half-Duplex Register (HAFDUP) ................................................................... 14-79
Maximum Frame Length Register (MAXFRM) ............................................. 14-80
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