MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1691

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Index
Freescale Semiconductor
buffer descriptors, 14-200–14-207
clocks
configuration of interfaces, 14-207–??
data width (POR), 4-20
error-handling, 14-175–14-176
eTSEC1 protocol (POR), 4-21
eTSEC3 protocol (POR), 4-21
features, 14-2
FIFO interface connections, 14-156
functional description, 14-146
gigabit Ethernet channel operation, 14-160
hash function
initialization/application information, 14-207–??
interrupts, 14-171–14-174
receive buffer descriptors (RxBD), 14-205
transmit buffer descriptors (TxBD), 14-202
inputs and outputs, 14-10
management clock out (EC_MDC), 14-11, 14-81
operation, 4-26
8-bit FIFO mode, 14-232
GMII interface mode, 14-212
MAC configuration, 14-71
MII interface mode, 14-208
RGMII interface mode, 14-220
RMII interface mode, 14-224
RTBI interface mode, 14-228
TBI interface mode, 14-216
8-bit encoded packet FIFO mode, 14-159
8-bit GMII-style packet FIFO mode, 14-158
CRC appending and checking, 14-157
flow control, 14-157
signal summary, 14-159
flow control, 14-170
frame reception, 14-163
frame recognition, 14-166
frame transmission, 14-162
initialization sequence, 14-160
internal and external loop back, 14-175
inter-packet gap time, 14-174
Magic Packet mode, 14-170
preamble customization, 14-164
RMON support, 14-166
algorithm, 14-168
registers, 14-115–14-116
gigabit Ethernet channel, 14-160
see also eTSEC, configuration
interrupt coalescing, 14-172
interrupt registers, 14-27–14-33
soft reset and reconfiguring procedure, 14-161
soft reset and reconfiguring procedure, 14-161
by frame count threshold, 14-172
by timer threshold, 14-173
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
EU
External system configuration
lossless flow control, 14-191
MAC functionality, 14-71–14-87
memory map/register definition, 14-14
modes of operation, 14-5
overview, 14-1
physical interface connections, 14-146
quality of service (QoS) support, 14-181–14-191
register descriptions, 14-26–14-146
signals, ??–14-13
signals<$startmode, 14-9
TCP/IP off-load, 14-176–14-181
access, 10-49
assignment status register, 10-50
back pressure determination and free buffers, 14-191
software use of hardware-initiated back pressure, 14-193
configuration, 14-71
CSMA/CD control, 14-71
handling packet collisions, 14-72
packet flow control, 14-72
PHY links control, 14-73
registers, 14-74–14-87
detailed memory map, 14-15–14-26
top-level module map, 14-15
RMON support, 14-87
gigabit media-independent interface (GMII), 14-148
media-independent interface (MII), 14-146
reduced gigabit media-independent interface (RGMII),
reduced media-independent interface (RMII), 14-146
reduced ten-bit interface (RTBI), 14-150
ten-bit interface (TBI), 14-149
receive queue filer, 14-183
transmission scheduling, 14-189
by acronym, see Register Index
DMA attribute registers, 14-118–14-120
FIFO registers, 14-116–14-118
general control and status registers, 14-26–14-40
hash function registers, 14-115–14-116
lossless flow control registers, 14-120–14-121
MAC registers, 14-74–14-87
MIB registers, 14-87–14-115
receive control and status registers, 14-53–14-70
ten-bit interface registers, 14-135–14-145
transmit control and status registers, 14-40–14-52
FIFO interface signal summary, 14-159
see also Signals, eTSEC
summary, 14-6
frame control blocks, 14-177
receive path off-load, 14-179
transmit path off-load, 14-178
14-148
Index-5
E–E