MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1560

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Device Performance Monitor
24.3.2.2
The performance monitor local control registers (PMLCAn and PMLCBn) are used to control the
operation of the PMCs. The performance monitor local control A and B registers are paired 32-bit control
registers that are associated with an individual counter to specify how the counter is used and what event
is monitored on that counter.
Figure 24-3
Table 24-3
24-6
6–31
Bits
1–4
0
5
Offset 0xE_1010
Reset
Name
W
R
FC
CE
—
—
FC
0
describes PMLCA0 fields.
shows the performance monitor local control A0 register (PMLCA0).
1
Freeze counter. Basic counter enable.
0 The PMCs are enabled and incremented (if permitted by other SPM control bits).
1 The PMCs are disabled–they do not increment.
Reserved
Condition enable. Controls counter overflow condition. Should be cleared when PMC0 is used as a trigger or is
selected for chaining.
0 Overflow conditions for PMC0 cannot occur (PMC0 cannot cause interrupts or freeze counters)
1 Overflow conditions occur when PMC0[msb] is set.
Reserved
Performance Monitor Local Control Registers (PMLCA n , PMLCB n )
—
Figure 24-3. Performance Monitor Local Control Register A0 (PMLCA0)
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
4
CE
5
6
Table 24-3. PMLCA0 Field Descriptions
All zeros
Description
—
Freescale Semiconductor
Access: Read/Write
31