MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 690

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Local Bus Controller
edges of LCLK, but continues to sample synchronous read data on rising edges of LCLK to maximize the
set-up margin for reads.
13.4.2
The GPCM allows a minimal glue logic and flexible interface to SRAM, EPROM, FEPROM, ROM
devices, and external peripherals. The GPCM contains two basic configuration register groups—BRn and
ORn.
Figure 13-34
mode. Byte-write enable signals (LWE) are available for each byte written to memory. Also, the output
enable signal (LOE) is provided to minimize external glue logic. On system reset, a global (boot)
chip-select is available that provides a boot ROM chip-select (LCS0) prior to the system being fully
configured.
13-48
General-Purpose Chip-Select Machine (GPCM)
shows a simple connection between an 8-bit port size SRAM device and the eLBC in GPCM
LCLK
LCLK
LCS n
LALE
LALE
LCS n
Figure 13-33. eLBC Bus Cycles in PLL-bypassed Mode (GPCM and UPM only)
LAD
Since LCLK is not used for NAND Flash EEPROMs controlled by FCM,
the eLBC drives and samples data on the same edge (rising edge when
LCRR[PBYP] = 0 and falling edge when LCRR[PBYP] = 1) on FCM
controlled banks.
LAD
TA
TA
Figure 13-32. eLBC Bus Cycles in PLL Mode (GPCM and UPM only)
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Address
t
t
LSKEW
LSKEW
Address
Write Data
Write Data
NOTE
read sample
Read Data
read sample
Read Data
point
point
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