MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 189

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.4.3.12
DDR3 requires a different voltage level from DDR2.
SDRAM type.
4.4.3.13
Three options are available for the frequency of the input SerDes2 reference clock: either a 100-MHz,
125-MHz, or 150-MHz LVDS differential clock.
This one clock is applied to an internal PLL whose output creates the clock used by all SGMII/SATA
SerDes lanes. The result is always a 1.25-Gbaud transmission/receive rate on each lane when used for
SGMII, and 1.5-Gbaud or 3.0-Gbaud when used for SATA. Note that the value latched on this signal
during POR is accessible through the memory-mapped
(PORDEVSR2).”
Freescale Semiconductor
TSEC3_TXD3,
PULSE_OUT2
LGPL0/LFCLE
TSEC_1588_
Default (11)
Functional
Functional
Default (1)
Signal
Signal
DDR SDRAM Type
Serdes 2 Reference Clock Configuration
cfg_srds2_ref_clk[0:1]
Reset Configuration
Reset Configuration
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
cfg_dram_type
Name
Name
Table 4-21. Serdes 2 Reference Clock Configuration
(Binary)
Value
Table 4-20. DDR DRAM Type
(Binary)
00
01
10
11
Value
0
1
Reserved
When configured for SATA: SerDes2 expects a 150-MHz reference clock
frequency.
This should not be used for when SerDes2 is configured for SGMII.
SerDes2 expects a 125-MHz reference clock frequency for either SATA or
SGMII functionality.
SerDes 2 expects a 100-MHz reference clock frequency for either SATA
or SGMII functionality (default).
DDR3
1.5 V, CKE low at reset
DDR2
1.8 V, CKE low at reset (default)
Table 4-20
Section 23.4.1.6, “POR Device Status Register 2
describes the configuration of the DDR
Meaning
Meaning
Reset, Clocking, and Initialization
4-19