MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 493

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 10-25
Freescale Semiconductor
Offset 0x3_4028
Reset
40-47
48-55
56-57
59-60
0–39
W
Bits
R
58
61
62
63
0
shows the AESU status register, and
Name
HALT
ICCR
OFL
IFL
RD
—
—
EI
DI
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
—
Table 10-26. AESU Status Register Field Descriptions
Reserved
The number of dwords currently in the output FIFO
The number of dwords currently in the input FIFO
Reserved
Halt. Indicates that the AESU has halted due to an error.
0 AESU not halted
1 AESU halted
Note: Because the error causing the AESU to stop operating may be masked before
Integrity Check Comparison Result
00 No integrity check comparison was performed.
01 The integrity check comparison passed.
10 The integrity check comparison failed.
11 Reserved
Note: A passed or failed result is generated only if the cipher mode with ICV checking is
Error interrupt: This status bit reflects the state of the error interrupt signal, as sampled by
the controller interrupt status register
(ISR)”).
0 AESU is not signaling error
1 AESU is signaling error
Done interrupt: This status bit reflects the state of the done interrupt signal, as sampled by
the controller interrupt status register
(ISR)”).
0 AESU is not signaling done
1 AESU is signaling done
Reset Done. This status bit, when high, indicates that AESU has completed its reset
sequence, as reflected in the signal sampled by the appropriate channel.
0 Reset in progress
1 Reset done
Note: This bit resets to 0 but has typically switched to 1 by the time a user checks the
reaching the interrupt status register, the AESU interrupt status register is used to
provide a second source of information regarding errors preventing normal
operation.
selected
register, indicating the EU is ready for operation.
Figure 10-25. AESU Status Register
39 40
OFL
Table 10-26
47 48
All zeros
(Section 10.5.4.2.2, “Interrupt Status Register
(Section 10.5.4.2.2, “Interrupt Status Register
IFL
Description
describes its fields.
55 56
—
57
HALT
58
59
ICCR
Security Engine (SEC) 3.0
60
Access: Read only
61
EI
DI
62
10-63
RD
63