MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 375

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.1.3.1
In mixed mode, external and internal interrupts are delivered using the normal priority and delivery
mechanisms detailed in
9.1.3.2
The PIC provides a mechanism to support alternate external interrupt controllers such as the
PC/AT-compatible 8259 interrupt controller architecture. After a hard reset, the PIC defaults to
pass-through mode, in which active-high interrupts from external source IRQ0 are passed directly to core 0
as shown in
external interrupt controller can be connected to IRQ0 and cause direct interrupts to the processor core 0.
The PIC does not perform a vector fetch from an 8259 interrupt controller.
When pass-through mode is enabled, the internally-generated interrupts shown in
forwarded to core 0. Instead, the PIC passes the raw interrupts from the internal sources to IRQ_OUT. Note
that when the PCI Express controller is configured as an endpoint (EP) device, the irq_out signal from the
PIC may used to automatically generate an outbound PCI Express MSI transaction toward the remote
interrupt controller resource on the root complex (RC). See
Generation.”
Note that in pass-through mode, interrupts generated within the PIC (global timers, interprocessor, and
message register interrupts) are disabled. If internal or PIC-generated interrupts must be reported internally
to the processor, mixed mode must be used.
9.1.4
The PIC can receive separate interrupts from the following sources:
Freescale Semiconductor
•
•
•
PC/AT-Compatible
PC/AT-Compatible
8259 Interrupt
8259 Interrupt
External—Off-chip signals, IRQ[]
Internal—On-chip sources from peripheral logic within the integrated device. See
Global timers A and B internal to the PIC
Controller
Controller
External
External
Interrupt Sources
Figure
Mixed Mode (GCR[M] = 1)
Pass-Through Mode (GCR[M] = 0)
IRQ[1:11]
9-2; all other external interrupt signals are ignored. Thus, the interrupt signal from an
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
(Disabled)
IRQ_OUT
Section 9.4.1, “Flow of Interrupt Control.”
IRQ0
Figure 9-2. Pass-Through Mode Example
Express
PCI
irq_out
GCR[M] = 0
PIC
Section 17.4.2.1.2, “Hardware MSI
int
Internal interrupts (see
Table
PIC-generated interrupts)
Programmable Interrupt Controller (PIC)
e500 Core
e500 Core
9-2) (not including
Table 9-3
Table
are not
9-2.
9-5