MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 852

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Three-Speed Ethernet Controllers
14.5.3.6.33 Transmit Multiple Collision Packet Counter (TMCL)
Figure 14-87
Table 14-91
14.5.3.6.34 Transmit Late Collision Packet Counter (TLCL)
Figure 14-88
Table 14-92
14-104
20–31
20–31
0–19
0–19
Bits
Bits
Offset eTSEC1:0x2_4700;
Reset
Offset
Reset
W
W
R
R
eTSEC3:0x2_6700
Name
Name
TMCL
TLCL
0
0
—
—
describes the fields of the TMCL register.
describes the fields of the TLCL register.
describes the definition for the TMCL register.
describes the definition for the TLCL register.
Figure 14-87. Transmit Multiple Collision Packet Counter Register Definition
Reserved
Transmit late collision packet counter. Increments for each frame transmitted which experienced a late
collision during a transmission attempt. Late collisions are defined using the collision window field of the
half-duplex [26:31] register.
Figure 14-88. Transmit Late Collision Packet Counter Register Definition
Reserved
Transmit multiple collision packet counter. Increments for each frame transmitted which experienced 2–15
collisions (including any late collisions) during transmission as defined using the
Half_Duplex[RETRANSMISSION MAXIMUM] field.
eTSEC1:0x2_4704;
eTSEC3:0x2_6704
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 14-91. TMCL Field Descriptions
Table 14-92. TLCL Field Descriptions
—
—
All zeros
All zeros
Description
Description
19 20
19 20
Freescale Semiconductor
TMCL
TLCL
Access: Read/Write
Access: Read/Write
31
31