MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 301

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 8-14
Freescale Semiconductor
11–15
16–19
20–24
9–10
Bits
4–5
6–8
0
1
2
3
DLL_RST_DIS
DQS_CFG
ODT_CFG
NUM_PR
FRC_SR
describes the DDR_SDRAM_CFG_2 fields.
SR_IE
Name
—
—
—
—
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Force self refresh
0 DDR controller operates in normal mode.
1 DDR controller enters self-refresh mode.
Self-refresh interrupt enable. The DDR controller can be placed into self refresh mode by forcing the
0 DDR controller does not enter self-refresh mode if panic interrupt is asserted.
1 DDR controller enters self-refresh mode if panic interrupt is asserted.
0 DDR controller issues a DLL reset to the DRAMs when exiting self refresh.
1 DDR controller does not issue a DLL reset to the DRAMs when exiting self refresh.
Reserved
DQS configuration
00 Reserved01Differential DQS signals are used for DDR2 support.
10 Reserved
11 Reserved
Reserved
“DDR Control Driver Register 1 (DDRCDR_1),”
00 Never assert ODT to internal IOs
01 Assert ODT to internal IOs only during writes to DRAM
10 Assert ODT to internal IOs only during reads to DRAM
11 Always keep ODT asserted to internal IOs
Reserved.
one time. Note that if posted refreshes are used, then this field, along with
DDR_SDRAM_INTERVAL[REFINT], must be programmed such that the maximum t
cannot be violated.
0000 Reserved
0001 1 refresh is issued at a time
0010 2 refreshes is issued at a time
0011 3 refreshes is issued at a time
...
1000 8 refreshes is issued at a time
1001–1111 Reserved
Reserved
DLL reset disable. The DDR controller typically issues a DLL reset to the DRAMs when exiting self
ODT configuration. This field defines how ODT is driven to the on-chip IOs. See
Number of posted refreshes. This determines how many posted refreshes, if any, can be issued at
PIC to assert IRQ_OUT. This is considered a ‘panic interrupt’ by the DDR controller, and it enters
self refresh as soon as possible. DDR_SDRAM_CFG[SREN] must also be set if the panic interrupt
is used.
refresh. However, this function may be disabled by setting this bit during initialization.
Table 8-14. DDR_SDRAM_CFG_2 Field Descriptions
Description
which defines the termination value that is used.)
DDR Memory Controller
Section 8.4.1.27,
ras
specification
8-27