MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 571

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.7.6.9
The MDEU interrupt mask register, shown in
given error (as defined in
this register is set, then the error is disabled; no error interrupt occurs and the interrupt status register is not
updated to reflect the error. If the corresponding bit is not set, then upon detection of an error, the interrupt
status register is updated to reflect the error, causing assertion of the error interrupt signal, and causing the
module to halt processing.
Offset 0x3_6038
Table 10-65
Freescale Semiconductor
W
R
58–60
62–63
0–48
Bits
Bits
0
57
61
49
50
51
describes MDEU interrupt status register fields.
MDEU Interrupt Mask Register
Table 10-65. MDEU Interrupt Status Register Field Descriptions (continued)
Name
Name
IFO
ICE
AE
—
—
—
—
IE
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 10-66. MDEU Interrupt Mask Register Field Descriptions
Section 10.7.6.8, “MDEU Interrupt Status
—
Address Error. An illegal read or write address was detected within the MDEU address
space.
0 No error detected
1 Address Error
Reserved
Input FIFO Overflow. The MDEU Input FIFO was pushed while full.
0 No overflow detected
1 Input FIFO has overflowed
Note: When operated through channel-controlled access, the SEC implements flow
Reserved
Reserved
Integrity Check Error. The supplied ICV did not match the one computed by the MDEU.
0 Integrity check error enabled. WARNING: Do not enable this if using EU status
1 Integrity check error disabled
Reserved
Internal Error. An internal processing error was detected while performing hashing.
0 Internal error enabled
1 Internal error disabled
Figure 10-90. MDEU Interrupt Mask Register
writeback (see bits IWSE and AWSE in
Register
control, and FIFO size is not a limit to data input size. When operated through
host-controlled access, the MDEU cannot accept FIFO inputs larger than 256
bytes without overflowing.
(CCR)”).
Figure
10-90, controls the result of detected errors. For a
48 49
ICE — IE ERE CE KSE DSE ME AE
Description
Description
50 51
Section 10.4.4.1, “Channel Configuration
52
Register”), if the corresponding bit in
53
54
55
56
Security Engine (SEC) 3.0
57 58
Access: Read/Write
—
60 61
IFO
10-141
62 63
—