MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1146

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MPC8536E-ANDROID

Manufacturer Part Number
MPC8536E-ANDROID
Description
HARDWARE/SOFTWARE ANDROID OS
Manufacturer
Freescale Semiconductor
Series
PowerQUICC ™r
Type
MPUr

Specifications of MPC8536E-ANDROID

Contents
Board
For Use With/related Products
MPC8536
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
PCI Express Interface Controller
17.3.8.1.8
The latency timer register, shown in
it is not used for PCI Express device functionality.
Table 17-44
17.3.8.1.9
The PCI Express header type register, shown in
compatible header.
Table 17-44
17-50
Offset 0x0D
Reset
Offset 0x0D
Reset
Bits
Bits
7–0
6–0
W
W
7
R
R Multifunction
Latency Timer Note that for PCI Express operation this register is ignored.
Multifunction Identifies whether a device supports multiple functions
describes the PCI Express latency timer register (PLTR).
describes the PCI Express header type register.
Header
Layout
7
7
Name
Name
PCI Express Latency Timer Register—0x0D
PCI Express Header Type Register—0x0E
Table 17-44. PCI Express Bus Latency Timer Register Field Descriptions
Table 17-45. PCI Express Bus Latency Timer Register Field Descriptions
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
0 Single function device
1 Multiple function device
0x00 Endpoint. See
0x01 Root Complex. See
All other encodings reserved.
6
Figure 17-44. PCI Express Bus Latency Timer Register
Figure 17-45. PCI Express Bus Latency Timer Register
Figure
Figure 17-46
17-44, is provided for legacy compatibility purposes (PCI 2.3);
Figure 17-58
Figure
0x00 (EP mode)
0x01 (RC mode)
Latency Timer
for type 0 layout.
All zeros
17-43, is used to identify the layout of the PCI
Header Layout
for type 1 layout.
Description
Description
Freescale Semiconductor
Access: Read only
Access: Read only
0
0

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