MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 416

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Offset MIDR0: 0x1610; MIDR1: 0x1630; MIDR2: 0x1650; MIDR3: 0x1670
Reset 0
Programmable Interrupt Controller (PIC)
9.3.7.6
The messaging interrupt destination registers (MIDRs), shown in
the messaging interrupts. Only one destination bit may be set; otherwise, behavior is undefined.
Table 9-43
9.3.8
The OpenPIC programming model supports multiprocessor systems of up to 32 separate processors. As
such, the OpenPIC interface specification provides for coordinating both the requesting and servicing of
interrupts among several processor cores within a single integrated device. To comply with the OpenPIC
specification, the PIC incorporates several of these multiprocessor capabilities.
9-46
12–15 PRIORITY Priority. Specifies the interrupt priority. The lowest priority is 0 and the highest priority is 15. A priority level
16–31 VECTOR Vector (Affects only interrupts routed to int ). Contains value returned when IACK is read and this interrupt
2–11
Bits
0–29
Bits
30
31
W
R
MIDR0: 0x1690; MIDR1: 0x16B0; MIDR2: 0x16D0; MIDR3: 0x16F0
1
0
Reserved in single-processor implementations.
Name
Name
—
0
1
P1
P0
—
describes the MIDRn fields.
Per-CPU (Private Access) Registers
Messaging Interrupt Destination Registers (MIDR0–MIDR7)
0
2
Note that these registers are meaningful only for interrupts routed to int.
Reserved, should be cleared.
of 0 inhibits signalling of this interrupt to the core. Affects only interrupts routed to int .
resides in the corresponding interrupt request register (IRR) for that core, as shown in
Reserved, should be cleared.
Processor core 1. Indicates whether processor core 1 receives the interrupt through int.
0 Processor core 1 does not receive this interrupt.
1 Directs the interrupt to processor core 1 through the assertion of int1 .
Note: Reserved in single-processor implementations.
Processor core 0. Indicates whether processor core 0 receives the interrupt.
0 Processor core 0 does not receive this interrupt.
1 Directs the interrupt to processor core 0 through the assertion of int0 .
The default destination is for processor core 0 to receive this external interrupt after the PIC is reset.
0
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Figure 9-43. Messaging Interrupt Destination Registers (MIDR n )
0
0
0
Table 9-42. MIVPR n Field Descriptions (continued)
0
0
Table 9-43. MIDR n Field Descriptions
0
0
0
0
0
NOTE
—
0
0
Description
Description
0
0
0
Figure
0
0
0
9-43, control the destination for
0
0
0
Freescale Semiconductor
0
0
Figure
Access: Read/Write
0
0
9-50.
29
0
P1
30
0
1
P0
31
1