MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1529

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

23.4.1.29 SerDes1 Control Register 2 (SRDS1CR2)
Shown in
lanes can be powered down using SRDSCR2[0:7]. It requires the entire SerDes1 to reset in order to
activate a lane from powering down.
Table 23-32
Freescale Semiconductor
Offset 0xE_3008
Reset
Reset
Bits
W
W
R
R
0
1
2
3
4
X3SG X3SH PPSEN
PDA
16
Figure
0
0
describes the fields of SRDS1CR2.
PDB
Name
17
PDC
PDD
PDA
PDB
PDE
1
0
23-29, SRDS1CR2 contains functional control bits for the SerDes1 logic. Individual
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
PDC
18
0
2
Figure 23-29. SerDes1 Control Register 2 (SRD1SCR2)
Lane A power down
0 Normal
1 Power down Lane A
Recommended setting per protocol:
PCI-Express: 0
Lane B power down
0 Normal
1 Power down Lane B
Recommended setting per protocol:
PCI-Express: 0
Lane C power down
0 Normal
1 Power down Lane C
Recommended setting per protocol:
PCI-Express: 0
Lane D power down
0 Normal
1 Power down Lane D
Recommended setting per protocol:
PCI-Express: 0
Lane E power down
0 Normal
1 Power down Lane E
Recommended setting per protocol:
PCI-Express: 0
PDD PDE PDF PDG PDH IPSEN
19
0
3
Table 23-32. SRDS1CR2 Field Descriptions
0
4
0
5
0
6
7
0
All zeros
8
0
Description
—
1
9
—
X3SA X3SB X3SC X3SD X3SE X3SF
10
0
11
0
12
0
Access: Read/Write
13
0
Global Utilities
14
0
15
31
0
23-37