MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 580

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Security Engine (SEC) 3.0
10.7.7.6
This status register contains six fields which reflect the state of PKEU internal fields.
The PKEU status register is read only. Writing to this location results in address error being reflected in
the PKEU interrupt status register.
Table 10-69
10-150
Offset 0x3_C028
Reset
W
R
8–63
0–55
Bits
Bits
0
62
63
56
57
describes the PKEU status register’s fields.
PKEU Status Register
Name
Name
Table 10-68. PKEU Reset Control Register Field Descriptions (continued)
SR
MI
—
—
Z
I
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 10-69. PKEU Status Register Field Descriptions
Module initialization. Module initialization is nearly the same as Software Reset, except
that the interrupt mask register remains unchanged. This module initialization includes
execution of an initialization routine, completion of which is indicated by the RESET_DONE
bit in the PKEU status register
0 Do not reset
1 Reset most of PKEU
SW reset. Software reset is functionally equivalent to hardware reset (the RESET# pin),
but only for the PKEU. All registers and internal state are returned to their defined reset
state. Upon negation of SW_RESET, the PKEU enters a routine to perform proper
initialization of the parameter memories. The RESET_DONE bit in the PKEU status
register indicates when this initialization routine is complete
Status
0 Do not reset
1 Full PKEU reset
Reserved
Reserved
Infinity. This bit reflects the state of the PKEU infinity detect bit when last sampled. Only
particular instructions within routines cause infinity to be modified, so this bit should be
used with great care.
Zero. This bit reflects the state of the PKEU zero detect bit when last sampled. Only
particular instructions within routines cause zero to be modified, so this bit should be used
with great care.
Register”).
Figure 10-99. PKEU Status Register
ID
All zeros
(Section 10.7.7.6, “PKEU Status
Description
Description
(Section 10.7.7.6, “PKEU
55 56 57
Register”).
I Z HALT
Freescale Semiconductor
58
Access: Read only
59 60 61 62 63
—
EI DI RD