MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 166

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MPC8536E-ANDROID

Manufacturer Part Number
MPC8536E-ANDROID
Description
HARDWARE/SOFTWARE ANDROID OS
Manufacturer
Freescale Semiconductor
Series
PowerQUICC ™r
Type
MPUr

Specifications of MPC8536E-ANDROID

Contents
Board
For Use With/related Products
MPC8536
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Signal Descriptions
pull-up resistors and must be driven high or low during the reset period. For details about all the signals
that require external pull-up resistors, see the MPC8536E Integrated Processor Hardware Specifications.
Note that the multiplexing of various signals on the MPC8536E is controlled by the PMUXCR register
described in
3-16
Ethernet Management
Functional Interface
Chapter 23, “Global Utilities.”
IEEE 1588
eTSEC1
eTSEC3
PCI
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 3-3. MPC8536E Reset Configuration Signals
PCI_GNT1
PCI_GNT2
EC_MDC
TSEC1_TXD[7:4]
TSEC1_TXD3
TSEC1_TXD2
TSEC1_TXD[1:0]
TSEC1_TX_ER
TSEC3_TXD7
TSEC3_TXD[6:4]
TSEC3_TXD3
TSEC3_TXD2
TSEC3_TXD[1:0]
TSEC3_TX_ER
TSEC_1588_TRIG_OUT[0:1]
TSEC_1588_CLK_OUT
TSEC_1588_PULSE_OUT1
TSEC_1588_PULSE_OUT2
Functional Signal Name
Reset Configuration
cfg_tsec1_prtcl[1:0]
cfg_tsec3_prtcl[1:0]
cfg_srds2_ref_clk0
cfg_srds2_ref_clk1
cfg_tsec1_reduce
cfg_tsec3_reduce
cfg_io_ports[0:2]
cfg_rom_loc[0:3]
cfg_srds2_prtcl0
cfg_srds2_prtcl1
cfg_srds2_prtcl2
cfg_ddr_pll[0:1]
cfg_eng_use0
cfg_eng_use1
cfg_eng_use2
cfg_pci_impd
cfg_ddr_pll2
cfg_pci_arb
Name
Freescale Semiconductor
Default
1111
111
11
11
1
1
1
1
1
1
1

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