MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 562

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Security Engine (SEC) 3.0
10.7.6
This section contains details about the Message Digest Execution Unit (MDEU), including modes of
operation, status and control registers, and FIFO.
Most of the registers described here would not normally be accessed by the host. They are documented
here mainly for debug purposes. In typical operation, the MDEU is used through channel-controlled
access, which means that most reads and writes of MDEU registers are directed by the SEC channels.
Driver software would perform host-controlled register accesses only on a few registers for initial
configuration and error handling.
10.7.6.1
This EU includes an ICV checking feature, that is, it can generate an ICV and compare it to another
supplied ICV. The pass/fail result of this ICV check can be returned to the host either by interrupt by a
writeback of EU status fields into host memory, but not by both methods at once.
To signal the ICV checking result by status writeback, turn on either the IWSE bit or AWSE bit in the
Channel Configuration Register (see
mask the ICE bit in the interrupt mask register
this case the normal done signaling (by interrupt or writeback) is undisturbed.
To signal the ICV checking result by interrupt, unmask the ICE bit in the interrupt mask register and turn
off the IWSE and AWSE bits in the Channel Configuration Register. If there is no ICV mismatch, then the
normal done signaling (by interrupt or writeback) occurs. When there is an ICV mismatch, there is an error
interrupt to the host, but no channel done interrupt or writeback.
10.7.6.2
The MDEU Mode Register is used to program the function of the MDEU. In channel-driven access, bits
56-63 of this register are specified by the user through the MODE0 or MODE1 field of the descriptor
header. The remaining two bits are supplied by the channel and thus are not under direct user control.
The two bits supplied by the channel are bits that control the meanings of other mode register fields. They
are the MDEU_B bit, and the NEW bit.
The MDEU_B bit determines which of two sets of algorithms is available through the ALG bits. The two
sets of algorithms are referred to as the MDEU-A set (MD5, SHA-1, SHA-224, and SHA-256) and the
MDEU-B set (SHA-224, SHA-256, SHA-384, and SHA-512). MDEU_B = 0 selects the MDEU-A set, and
MDEU_B = 1 selects the MDEU-B set. In channel-driven operation, the MDEU_B mode bit is supplied
by the channel, based on the EU_SEL field of the descriptor header, where the user can choose MDEU-A
or MDEU-B (see
The NEW bit determines the configuration of other mode register fields as shown in
Figure
1001_1). The old configuration (NEW=0) is used by all other descriptor types. The old configuration is
the same as the one used in SEC 2.0, except for the CICV and SMAC bits. When MDEU is configured by
the Polychannel, the value of NEW is determined by the descriptor type field of the descriptor header.
10-132
10-84. The “new” configuration (NEW=1) is used only by TLS/SSL descriptor types (1000_1,
Message Digest Execution Unit (MDEU)
ICV Checking in MDEU
MDEU Mode Register
Table
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
10-6).
Section 10.4.4.1, “Channel Configuration Register
(Section 10.7.6.9, “MDEU Interrupt Mask
Freescale Semiconductor
Figure 10-83
(CCR)”), and
Register”). In
and