MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1128

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PCI Express Interface Controller
17.3.6.2
The PCI Express error interrupt enable register, shown in
when the corresponding PCI Express error detect register bits are set.
17-32
Offset 0xE08
Reset
Reset
24–31
Bits
17
18
19
20
21
22
23
W
W
R
R CRST
IE
16
0
Name
IOIEP
CIEP
OAC
IOIS
IOIA
MIS
CIS
—
PCI Express Error Interrupt Enable Register (PEX_ERR_EN)
MIS
Table 17-23. PCI Express Error Detect Register Field Descriptions (continued)
17
IE
Figure 17-25. PCI Express Error Interrupt Enable Register (PEX_ERR_EN)
Message invalid size. An outbound message transaction that is greater than 4 bytes or crosses a 4-byte
boundary was detected. See
information.
1 An invalid size outbound message transaction was detected
0 No invalid size outbound message transaction detected
I/O invalid size. An outbound I/O transaction that is greater than 4 bytes or crosses a 4-byte boundary was
detected.
1 an invalid size outbound I/O transaction was detected
0 no invalid size outbound I/O transaction detected
Configuration invalid size. An outbound configuration transaction that is greater than 4 bytes or crosses a
4-byte boundary was detected.
1 An invalid size outbound configuration transaction was detected
0 No invalid size outbound configuration transaction detected
Configuration invalid EP. An outbound ATMU configuration transaction request was seen when in EP
mode.
1 An outbound configuration transaction while in EP was detected
0 No outbound configuration transaction in EP detected
I/O invalid EP. An outbound I/O transaction request was seen when in EP mode.
1 An outbound I/O transaction while in EP was detected
0 No outbound I/O transaction in EP detected
Outbound ATMU crossing. An outbound crossing ATMU transaction was detected.
1 An outbound transaction that hits in one window and crosses overing it was detected
0 No outbound ATMU crossing condition detected
I/O invalid address. An outbound I/O transaction with a translated address of greater than 4 Gbytes was
detected.
1 A greater than 4-Gbyte I/O address was detected
0 No greater than 4-Gbyte I/O address detected
Reserved
IOIS
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
18
IE
CIS
IE
19
—
CIEP
20
IE
IOIEP
IE
21
Section 17.4.1.9.1, “Outbound ATMU Message
OAC
22
IE
IOIA
23
IE
7
All zeros
All zeros
PCT
Description
IE
24
8
Figure
—
9
17-25, allows interrupts to be generated
PCAC
IE
10
PNM
11
IE
—
CDNSC
Generation,” for more
12
IE
Freescale Semiconductor
CRSNC
Access: Read/Write
IE
13
ICCA
IE
14
IACA
15
IE
31