MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 441

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The CRC algorithm treats a message stream of bits as coefficients of a massive polynomial and computes
the remainder of the modulo two division by an order 32 divisor polynomial. The divisor polynomial is
specific to the protocol and chosen to conform to certain mathematical properties to ensure that single bit
errors can be detected. Cyclic redundancy codes are used to ensure data integrity over potentially
unreliable channels. There are two major CRC protocol algorithms: CRC32 and CRC32C. IEEE 802
defines the CRC32 algorithm, while iSCSI defines the CRC32C algorithm. Both protocols bit swap, byte
swap, and then complement the calculated remainder to generate the checksum. The CRCU is designed to
support the following check algorithms:
The CRCU can perform ICV checking by computing a raw CRC across a message and
previously-calculated CRC. Integrity is verified if the result matches the polynomial specific residue.
For more information about the unit’s operation, refer to
Unit (CRCU).”
10.1.4.8
The RNGU is a functional block that generates 64-bit random numbers and stores them in an output FIFO.
Because many cryptographic algorithms use random numbers as a source for generating a secret value (a
nonce), it is desirable to have a private RNG for use by the SEC. The anonymity of each random number
must be maintained, as well as the unpredictability of the next random number. The FIPS-140 ‘common
criteria’-compliant private RNG allows the system to develop random challenges or random secret keys.
The secret key can thus remain hidden from even the high-level application code, providing an added
measure of physical security.
For more information about the unit’s operation, refer to
(RNGU).”
10.2
Table 10-2
All address gaps in
These address values are offsets from the SoC’s base address register (consult the SoC documentation for
specific register name).
Freescale Semiconductor
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CRC32 algorithm specified in IEEE 802.1.
CRC32C algorithm specified in RFC3385.
A programmable polynomial mode with optional remainder bit mangling is also supported, which
can be used to implement proprietary protocols.
Configuration of Internal Memory Space
gives the base address map, and shows the blocks of addresses assigned to each SEC sub-block.
Random Number Generator Unit (RNGU)
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 10-2
are reserved for future use. The 18-bit SEC address bus value is shown.
Section 10.7.8, “Random Number Generator Unit
Section 10.7.3, “Cyclical Redundancy Check
Security Engine (SEC) 3.0
10-11