MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1666

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Revision History
8.4.1.27, 8-47
8.4.1.27, 8-47
8.4.1.28, 8-50
8.6.1, 8-91
8.6.2, 8-93
9.3.1.3, 9-20
9.3.7.6, 9-46
10.3.5, 10-30
10.7.1.11., 10-74
13.4.1.8, 13-48
B-2
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Added note to this section:
All driver calibration, whether by software or hardware, should be done before the
DDR controller is enabled (before DDR_SDRAM_CFG[MEM_EN] is set).
In
ODT as follows:
001: changed from 46 Ohms to 55 Ohms
011: changed from 43 Ohms to 50 Ohms
101: changed from 33 Ohms to 43 Ohms
Also added clarification to DDRCDR_1[ODT] that the ODT value (which is
obtained by concatenating DDRCDR_1[ODT] and DDRCDR_2[ODT]) is
obtained as follows:
Note that the order of concatenation is (from left to right)
DDRCDR_1[ODT], DDRCDR_2[ODT]
In
ODT as follows:
001: changed from 46 Ohms to 55 Ohms
011: changed from 43 Ohms to 50 Ohms
101: changed from 33 Ohms to 43 Ohms
Also added clarification to DDRCDR_2[ODT] that the ODT value (which is
obtained by concatenating DDRCDR_1[ODT] and DDRCDR_2[ODT]) is
obtained as follows:
Note that the order of concatenation is (from left to right)
DDRCDR_1[ODT], DDRCDR_2[ODT]
Updated DQS_CFG configuration row. Specifically, DDR2 configuration
formerly read:
‘Can be set to either 00 or 01, depending on if differential strobes are used’
now reads:
‘Should be set to 01’
Added clarification that DDR3 specification requires additional delay by adding
the phrase “500 ms for DDR3” to the second sentence of the first paragraph of this
section, as follows:
“Note that 200 ms (500 ms for DDR3) must elapse after DRAM clocks are
stable...”
Changed reset value of FRR[NIRQ] from 0x6B to 0x67
Removed fields EP, CI0 and CI1
In Table 10-10, “Descriptor Format Summary,” updated row for KEU f9
Added note that AES-CCM does not support zero-length AAD and payload
simultaneously
Updated Figure 13-33, “eLBC Bus Cycles in PLL and PLL-bypassed Modes
(GPCM and UPM only),” to show LCSn deasserted one-half LCLK cycle later
Table
Table
8-33, “DDRCDR_1 Field Descriptions,” updated some settings for field
8-34, “DDRCDR_2 Field Descriptions,” updated some settings for field
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