MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1224

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

0 1 2 3
Data 0 LS Byte LSB0
0 1 2 3 4 5 6
MSB0
Enhanced Serial Peripheral Interface
A transaction can be full duplex (regular eSPI) or half duplex. Half duplex can be used for example for
write accesses to a flash (only transmit) or for a read access from a flash (first part is transmit without
receive, while the second part is receive without transmit).
18.3.1.5
The 32-bit write-only eSPI transmit FIFO access register (SPITF) holds the characters to be written to the
transmit FIFO. The number of bits in each character is specified by SPMODEx[LENx]. Each time
SPIE[TNF] is set, the core can write more data to the SPITF register, if there is no error indication in the
SPIE.
For character lengths of 4 to 8 bits, SPITF contains up to 4 characters (unless end of frame). The lsbs are
in bits 7, 15, 23, and 31 of SPITF.
For character lengths of 9 to 16 bits, SPITF contains up to 2 characters (unless end of frame). For 16 bits
with SPMODEx[REVx]=1, the lsb is in bits 15 and 31 of SPITF. For other options, lsbs are in bits 7 and
23 while msbs are in bits (23–LENx) and (39–LENx) of SPITF.
Example : REV=0, LEN=10 (0xA), SPITF[0–15] = 0xFB05—bitstream is : (lsb first) 11011111101 (msb
last).
Note—The user must write N bytes of SPITF (1<=N<=4) that do not exceed the number of free bytes in
the transmit FIFO. It is valid for the user to write only 1 or 2 bytes of SPITF (at offset 0x010) if the user
wishes to write fewer characters than the maximum supported by SPITF for the particular character length
in use.
Figure 18-7
The following figures show examples of the contents of SPITF with various parameters set.
18-10
Offset 0x010
Reset
—
0
W
R
MSB0 Data 0 LSB0
1 2 3 4 5 6
0
4
Data 0
Figure 18-10. SPITF Example—SPMODEx[REVx]=0, SPMODEx[LENx]=10, LSB Sent First
Figure 18-8. SPITF Example—SPMODEx[REVx]=0, SPMODEx[LENx]=3, LSB Sent First
shows the eSPI transmit data register.
5
eSPI Transmit FIFO Access Register (SPITF)
7
6
LSB0 MSB1
Figure 18-9. SPITF Example—SPMODEx[REVx]=x, SPMODEx[LENx]=7
7
8
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
7
9 10 11 12
—
8 9 10 11
8
—
Figure 18-7. eSPI Transmit Data Register (SPITF)
9 10 11 12 13 14
MSB0 Data 0 MS Byte
MSB1 Data 1 LSB1
13
Data 1
12
13
14
14
LSB1 MSB2
15
15
15
16 17 18 19
16 17 18 19 20 21 22
16
All zeros
Data 1 LS Byte
DATA
—
17 18 19 20 21 22
MSB2 Data 2 LSB2
Data 2
20
21
LSB1
22
23
LSB2 MSB3
23
24 25 26 27 28
23
24 25 26 27
—
24
—
Freescale Semiconductor
25 26 27 28 29 30
MSB1 Data 1 MS Byte
29
MSB3 Data 3 LSB3
Access: Write only
Data 3
28
29
30
30
LSB3
31
31
31
31