MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 660
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MPC8536E-ANDROID
Manufacturer Part Number
MPC8536E-ANDROID
Description
HARDWARE/SOFTWARE ANDROID OS
Manufacturer
Freescale Semiconductor
Series
PowerQUICC ™r
Type
MPUr
Datasheets
1.MPC8536EBVTAVLA.pdf
(127 pages)
2.MPC8536EBVTAVLA.pdf
(2 pages)
3.MPC8536EBVTAVLA.pdf
(1706 pages)
Specifications of MPC8536E-ANDROID
Contents
Board
For Use With/related Products
MPC8536
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- Current page: 660 of 1706
- Download datasheet (15Mb)
Enhanced Local Bus Controller
13-18
25–27
Bits
24
28
29
Name
TRLX
CHT
SCY
RST
Command hold time. Determines the LFWE negation prior to the command, address, or data change when
the external memory access is handled by the FCM.
Cycle length in bus clocks. Determines:
000 No extra wait states
001 1 bus clock cycle wait state
...
111 7 bus clock cycle wait states
Read setup time. Determines the delay of LFRE assertion relative to sampling of read data when the
external memory access is handled by the FCM.
Timing relaxed. Modifies the settings of timing parameters for slow memories.
0 Normal timing is generated by the FCM.
1 Relaxed timing on the following parameters:
• the number of wait states inserted in command, address, or data transfer bus cycles, when the FCM
• the delay between command/address writes and data write cycles, or the delay between write cycles and
• the delay between a command write and the first sample point of the RDY/BSY pin (connected to LFRB).
• Doubles the number of clock cycles between LCS n assertion and commands.
• Doubles the number of wait states specified by SCY, providing up to 14 wait states.
• Works in conjunction with CST and RST to extend command/address/data setup times.
• Adds one clock cycle to the command/address/data hold times.
• Works in conjunction with CBT to extend the wait time for read/busy status sampling by 16 clock cycles.
• Works in conjunction with EHTR to double hold time on read accesses.
handles the external memory access. Thus it is the main parameter for determining cycle length. The
total cycle length depends on other timing attribute settings.
read cycles from NAND Flash EEPROM. A delay of 4×(2+SCY) clock cycles (TRLX = 0) or 8×(2+SCY)
clock cycles (TRLX = 1) is inserted between the last write and the first data transfer to/from NAND Flash
devices.
LFRB is not sampled until 8×(2+SCY) clock cycles (TRLX = 0) or 16×(2+SCY) clock cycles (TRLX = 1)
have elapsed following the command.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
TRLX
TRLX
0
0
1
1
0
0
1
1
Table 13-8. OR n
CHT
RST
0
1
0
1
0
1
0
1
The write-enable is negated 0.5 clock cycles before any command, address, or
data change.
The write-enable is negated 1 clock cycle before any command, address, or data
change.
The write-enable is negated 1.5 clock cycles before any command, address, or
data change.
The write-enable is negated 2 clock cycles before any command, address, or data
change.
The read-enable is asserted 0.75 clock cycles prior to any wait states.
The read-enable is asserted 1 clock cycle prior to any wait states.
The read-enable is asserted 0.5 clock cycles prior to any wait states.
The read-enable is asserted 1 clock cycle prior to any wait states.
—
FCM Field Descriptions (continued)
Description
Meaning
Meaning
Freescale Semiconductor
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