MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 473

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.4.4.3
The CDPR reflects the value of the head end of the fetch FIFO, which contains the address of the descriptor
which the channel is currently processing.
CPDR fields are shown in
Freescale Semiconductor
Offset Channel 1: 0x3_1140, Channel 2: 0x3_1240,
Reset
CSR Bit #
51-52
W
R
48
49
50
53
54
55
56
57
58
59
Channel 3: 0x3_1340, Channel 4: 0x3_1440
0
MDTE Master Data Transfer Error. When the SEC, while acting as a bus master, detects an error, the controller
SGLM Scatter/Gather Length Mismatch. Indicates the total data size covered by a gather link table did not
Name
WDT
RSG
DOF
SOF
EUE
Current Descriptor Pointer Register (CDPR)
IDH
RSI
ID_TAG
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Double Fetch FIFO write overflow error. This bit is set when the channel fetch FIFO is full, SOF is set,
and another write has been made to the fetch FIFO. This error halts the channel. To clear this error, the
host must write a ‘1’ to this bit.
Single Fetch FIFO write overflow error. This bit is set when the channel fetch FIFO is full and another
write has been made to the fetch FIFO. The channel continues processing, but the descriptor pointer is
lost. To clear this error, the host must write a ‘1’ to this bit.
passes this error to the channel. This error halts the channel. Restarting the channel clears this bit.
Reserved
Illegal descriptor header. Possible causes of an illegal descriptor header are:
This error halts the channel. Restarting the channel clears this bit.
Reserved
EU error. An EU assigned t o t hi s channel has generated an error interrupt. This error may also be
reflected in the controller's interrupt status register. This error halts the channel. To clear this error, the
host must clear the error source in the EU that produced the error.
Watchdog timeout. The main state machine stayed asleep too long. This timer runs only after EUs have
been reserved, and does not run if the primary EU is the RNGU or PKEU. The timeout interval is
controlled by the FCC field of the Channel Configuration Register. This error halts the channel.
Restarting the channel clears this bit.
match the total data size from the main descriptor. This error halts the channel. Restarting the channel
clears this bit.
RAID Size Incorrect. The channel was provided with a descriptor of type RAID_XOR with data sizes not
permitted. To clear this error, the host must write a ‘1’ to this bit.
RAID Scatter Gather Error. The channel was provided with a descriptor of type RAID_XOR with a j bit
set. Use of scatter/gather is not permitted with RAID_XOR type descriptors. To clear this error, the host
must write a ‘1’ to this bit.
• Invalid primary EU indicated by op0 field in descriptor header.
• Invalid secondary EU indicated by op1 field in descriptor header.
Table 10-15. Channel Status Register Error Field Definitions
15 16
Figure
Figure 10-13. Current Descriptor Pointer Register
10-13, and described in
—
27 28
EPTR
All zeros
31 32
Table
Error
10-16.
CUR_DES_PTR_ADRS
Security Engine (SEC) 3.0
Access: Read only
10-43
63