MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 641

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

is cleared when the trigger level or a time-out has been reached and it is set when there are no more
characters in the receiver FIFO.
The UDSR[TXRDY] bit reflects the status of the transmitter FIFO or UTHR. In mode 0 (UFCR[DMS] is
cleared), UDSR[TXRDY] is cleared when there are no characters in the transmitter FIFO or UTHR and it
is set after the first character is loaded into the transmitter FIFO or UTHR. This occurs regardless of the
setting of the UFCR[FEN] bit. In mode 1 (UFCR[DMS] and UFCR[FEN] are set), UDSR[TXRDY] is
cleared when there are no characters in the transmitter FIFO or UTHR and it is set when the transmitter
FIFO is full.
See
USDR[RXRDY] and USDR[TXRDY] bits.
12.4.5.3
An interrupt is active when DUART interrupt ID register bit 7 (UIIR[IID0]), is cleared. The interrupt
enable register (UIER) is used to mask specific interrupt types. For more details refer to the description of
UIER in
When the interrupts are disabled in UIER, polling software cannot use UIIR[IID0] to determine whether
the UART is ready for service. The software must monitor the appropriate bits in the line status (ULSR)
and/or the modem status (UMSR) registers. UIIR[IID0] can be used for polling if the interrupts are enabled
in UIER.
12.5
The following requirements must be met for DUART accesses:
A system reset puts the DUART registers to a default state. Before the interface can transfer serial data,
the following initialization steps are recommended:
Freescale Semiconductor
•
•
1. Update the programmable interrupt controller (PIC) DUART channel interrupt vector source
2. Set data attributes and control bits in the ULCR, UFCR, UAFR, UMCR, UDLB, and UDMB.
3. Set the data attributes and control bits of the external modem or peripheral device.
4. Set the interrupt enable register (UIER).
5. To start a write transfer, write to the UTHR.
6. Poll UIIR if the interrupts generated by the DUART are masked.
Section 12.3.1.13, “DMA Status Registers (UDSRn),”
All DUART registers must be mapped to a cache-inhibited and guarded area. (That is, the WIMG
setting in the MMU needs to be 0b01X1.)
All DUART registers are 1 byte wide. Reads and writes to these registers must be byte-wide
operations.
registers.
Section 12.3.1.4, “Interrupt Enable Register (UIER) (ULCR[DLAB] = 0).”
DUART Initialization/Application Information
Interrupt Control Logic
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
for a complete description of the
DUART
12-23