MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 733

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

should not be used from LAD[27:31]. All other address bits, A[0:26], must be reconstructed through the
latch, as shown in
13.5.1.2
To achieve the highest possible bus speeds on the local bus, it is recommended to reduce the number of
devices connected directly to the bus. For best results, only one bank of synchronous SRAMs should have
a direct connection, and a bus demultiplexor should be used to replace separate latch and separate bus
transceiver combinations.
guideline, and the board designer must simulate the electric characteristics of the scenario to determine the
maximum operating frequency.
Freescale Semiconductor
Local Bus Interface
Local Bus Interface
Peripheral Hierarchy on the Local Bus for High Bus Speeds
Figure
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
LAD[0:31]
LA[27:31]
Figure 13-72. Local Bus Peripheral Hierarchy for High Bus Speeds
Figure 13-71. Multiplexed Address/Data Bus for 32-Bit Addressing
LBCTL
LALE
LAD n
LALE
LA n
13-71.
Figure 13-72
LAD[0:26]
Muxed Address/Data
Unmuxed Address
Muxed Address/Data
Unmuxed Address
shows an example of such a hierarchy. This section is only a
Buffered Data
A/D
LE
DIR
D
LE
Latch
Latch
Q
Q
B
A
DQ
MA
Peripherals
Memories
Slower
and
D[31:0]
A[31:5]
A[4:0]
A
DQ
Enhanced Local Bus Controller
SSRAM
Device
13-91