MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 319

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 8-28
8.4.1.24
The DDR Register Control Word 2register should be programmed with the intended values of the register
control words if DDR_SDRAM_CFG[RCW_EN] is set. Each 4-bit field represents the value that is placed
on MA[3], MA[4], MBA[0], and MBA[1] during register control word writes.
Table 8-28
Freescale Semiconductor
Offset 0x184
Reset
t
12–15
16–19
20–23
24–27
28–31
8–11
8–11
Bits
Bits
0–3
4–7
0–3
4–7
W
R
0
RCW8
describes the DDR_SDRAM_RCW_1 fields.
describes the DDR_SDRAM_RCW_2 fields.
RCW10
RCW0
RCW1
RCW2
RCW3
RCW4
RCW5
RCW6
RCW7
RCW8
RCW9
Name
DDR SDRAM Register Control Word 2 (DDR_SDRAM_RCW_2)
Name
3
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
4
Figure 8-25. DDR Register Control Word 2 (DDR_SDRAM_RCW_2)
RCW9
Table 8-29. DDR_Register Control Word 1 Field Descriptions
Table 8-30. DDR_Register Control Word 2 Field Descriptions
Register Control Word 0. Represents the value that is placed on MBA[1], MBA[0], MA[4], and
MA[3] during writes to register control word 0.
Register Control Word 0. Represents the value that is placed on MBA[1], MBA[0], MA[4], and
MA[3] during writes to register control word 1.
Register Control Word 0. Represents the value that is placed on MBA[1], MBA[0], MA[4], and
MA[3] during writes to register control word 2.
Register Control Word 0. Represents the value that is placed on MBA[1], MBA[0], MA[4], and
MA[3] during writes to register control word 3.
Register Control Word 0. Represents the value that is placed on MBA[1], MBA[0], MA[4], and
MA[3] during writes to register control word 4.
Register Control Word 0. Represents the value that is placed on MBA[1], MBA[0], MA[4], and
MA[3] during writes to register control word 5.
Register Control Word 0. Represents the value that is placed on MBA[1], MBA[0], MA[4], and
MA[3] during writes to register control word 6.
Register Control Word 0. Represents the value that is placed on MBA[1], MBA[0], MA[4], and
MA[3] during writes to register control word 7.
Register Control Word 0. Represents the value that is placed on MBA[1], MBA[0], MA[4], and
MA[3] during writes to register control word 8.
Register Control Word 0. Represents the value that is placed on MBA[1], MBA[0], MA[4], and
MA[3] during writes to register control word 9.
Register Control Word 0. Represents the value that is placed on MBA[1], MBA[0], MA[4], and
MA[3] during writes to register control word 10.
7
8
RCW10
11 12
RCW11
All zeros
15 16
RCW12
Description
Description
19 20
RCW13
23 24
RCW14
DDR Memory Controller
Access: Read/Write
27 28
RCW15
8-45
31