MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 581

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.7.7.7
The interrupt status register indicates which unmasked errors have occurred and have generated error
interrupts to the channel. Each bit in this register can only be set if the corresponding bit of the PKEU
interrupt mask register is zero (see
If the PKEU interrupt status register is non-zero, the PKEU halts and the PKEU error interrupt signal is
asserted to the controller (see
PKEU is being operated through channel-controlled access, then an interrupt signal is generated to the
channel to which this EU is assigned. The EU error then appears in bit 55 of the channel status register
(see
If the interrupt status register is written from the host, 1s in the value written are recorded in the interrupt
status register if the corresponding bit is unmasked in the interrupt mask register. All other bits are cleared.
This register can also be cleared by setting the RI bit of the PKEU reset control register.
The fields of the PKEU interrupt status register are shown in
Freescale Semiconductor
Table
59-60
Bits
58
61
62
63
10-15) and generates a channel error interrupt to the controller.
PKEU Interrupt Status Register
Name
HALT
RD
—
EI
DI
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 10-69. PKEU Status Register Field Descriptions (continued)
Halt indicates that the PKEU has halted due to an error.
0 PKEU not halted
1 PKEU halted
Note: Because the error causing the PKEU to stop operating may be masked before
Reserved
Error interrupt: This status bit reflects the state of the error interrupt signal, as sampled by
the controller interrupt status register
(ISR)”).
0 PKEU is not signaling error
1 PKEU is signaling error
Done interrupt: This status bit reflects the state of the done interrupt signal, as sampled by
the Controller interrupt status register
(ISR)”).
0 PKEU is not signaling done
1 PKEU is signaling done
Reset Done. This status bit, when high, indicates that PKEU has completed its reset
sequence, as reflected in the signal sampled by the appropriate channel.
0 Reset in progress
1 Reset done
Note: Reset Done resets to 0, but has typically switched to 1 by the time a user checks the
Section 10.5.4.2.2, “Interrupt Status Register
reaching the interrupt status register, the PKEU interrupt status register is used to
provide a second source of information regarding errors preventing normal
operation.
register, indicating the EU is ready for operation.
Section 10.7.7.8, “PKEU Interrupt Mask
(Section 10.5.4.2.2, “Interrupt Status Register
(Section 10.5.4.2.2, “Interrupt Status Register
Description
Figure
10-100, and described in
(ISR)”). In addition, if the
Register”).
Security Engine (SEC) 3.0
Table
10-70.
10-151