MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 875

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 14-118
14.5.3.11.5 Timer Event Mask Register (TMR_PEMASK)
Timer event mask register. The event mask register provides control over which possible interrupt events
in the TMR_PEVENT register are permitted to participate in generating hardware interrupts to the PIC.
All implemented bits in this register are R/W and cleared upon a hardware reset.
the definition for the TMR_PEMASK register.
Freescale Semiconductor
Offset eTSEC1:0x2_4E10
Reset
Reset
24–30
0–21
Bits
Offset eTSEC1:0x2_4E0C
Reset
Reset
22
23
31
W
W
R
R
W
W
R
R
16
0
16
0
Name
TXP2
TXP1
RXP
describes the fields of the TMR_PEVENT register fields for the timer.
—
—
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Reserved
Indicates that a PTP frame has been transmitted and its timestamp is stored in TXTS2 register.
0 PTP packet not transmitted
1 PTP packet has been transmitted
Indicates that a PTP frame has been transmitted and its timestamp is stored in TXTS1 register.
0 PTP packet not transmitted
1 PTP packet has been transmitted
Reserved
Indicates that a PTP frame has been received
0 PTP packet not received
1 PTP packet has been received
—
Table 14-118. TMR_PEVENT Register Field Descriptions
—
Figure 14-113. TMR_PEMASK Register Definition
Figure 14-112. TMR_PEVENT Register Definition
21
21
TXP2EN TXP1EN
22
TXP2
22
All zeros
All zeros
All zeros
All zeros
—
—
TXP1
23
23
Description
24
24
Enhanced Three-Speed Ethernet Controllers
—
—
Figure 14-113
Access: Read/Write
Access: Read/Write
30
30
describes
RXP
RXPEN
15
31
14-127
15
31