MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1149

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 17-48
Base address register 3 at offset 0x1C and base address register 5 at offset 0x24 are used to define the upper
portion of the 64-bit inbound memory windows. The 64-bit high memory BARs are shown in
Figure
Table 17-49
Freescale Semiconductor
Offset 0x18 (EP-mode only)
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
31–0 ADDRESS Indicates the upper portion of the base address where the inbound memory window begins. The number of
31–12 ADDRESS Indicates the lower portion of the base address where the inbound memory window begins. The number
Bits
Offset 0x1C (EP-mode only)
Reset
11–4
Bits
2–1
3
0
W
R
W
R
0x20 (EP-mode only)
31
0x24 (EP-mode only)
17-50.
31
Name
MemSp
Name
PREF
TYPE
—
describes the PCI Express 64-bit low memory BAR fields.
describes the PCI Express 64-bit low memory BAR fields.
Table 17-48. 64-Bit Low Memory Base Address Register Field Descriptions
bits that the device allows to be writable is selected through the inbound window size in the inbound window
attributes registers (PEXIWAR2 for offset 0x1C and PEXIWAR3 for offset 0x24). If no access to local
memory is to be permitted by external requestors, then all bits are programmed.
Table 17-49. Bit Setting for 64-Bit High Memory Base Address Register
of bits that the device allows to be writable is selected through the inbound window size in the inbound
window attributes registers (PEXIWAR2 for offset 0x18 and PEXIWAR3 for offset 0x20).
Reserved. The device allows a 4 Kbyte window minimum.
Prefetchable. This bit is determined by PEXIWAR n [2].
Type.
0b10 Locate anywhere in 64-bit address space.
Memory space indicator
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Figure 17-50. 64-Bit High Memory Base Address Register
Figure 17-49. 64-Bit Low Memory Base Address Register
ADDRESS
ADDRESS
All zeros
Description
Description
12 11
—
4
PCI Express Interface Controller
PREF
1
3
Access: Read/Write
1
2
TYPE
Access: Mixed
0
1
MemSp
17-53
0
0
0