MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1074

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PCI Bus Interface
For linear incrementing mode, the memory address is encoded/decoded using PCI_AD[31:2]. Thereafter,
the address is incremented by 4 bytes after each data phase completes until the transaction is terminated
or completed (a 4-byte data width per data phase is implied). Note that the two low-order bits on the
address bus are included in all parity calculations.
For cache wrap mode (PCI_AD[1:0] = 0b10) reads, the critical memory address is decoded using
PCI_AD[31:2]. The address is incremented by 4 bytes after each data phase completes until the end of the
cache line is reached. For cache-wrap reads, the address wraps to the beginning of the current cache line
and continues incrementing until the entire cache line (32 bytes) is read. The PCI controller does not
support cache-wrap write operations and executes a target disconnect after the data phase for the end of
the cache line completes for writes with PCI_AD[1:0] = 0b10. That is, the PCI controller does not wrap
back to the beginning of the cache line. Note that the two low-order bits on the address bus are included
in all parity calculations.
16.4.2.3.2
For PCI I/O accesses, 32 address signals (PCI_AD[31:0]) are used to provide a byte address. After a target
has claimed an I/O access, it must determine if it can complete the entire access as indicated by the byte
enable signals. If all the selected bytes are not in the address range of the target, the entire access cannot
complete. In this case, the target does not transfer any data and terminates the transaction with a
target-abort error. See
16.4.2.3.3
PCI supports two types of configuration accesses that use different formats for the PCI_AD[31:0] signals
during the address phase. The two low-order bits of the address indicate the format used for the
configuration address phase—type 0 (PCI_AD[1:0] = 0b00) or type 1 (PCI_AD[1:0] = 0b01). Both
address formats identify a specific device and a specific configuration register for that device. See
Section 16.4.2.11, “Configuration Cycles,”
16.4.2.4
The PCI_DEVSEL signal is driven by the target of the current transaction. PCI_DEVSEL indicates to the
other devices on the PCI bus that the target has decoded the address and claimed the transaction.
PCI_DEVSEL may be driven one, two, or three clock cycles (fast, medium, or slow device select timing)
following the address phase. Device select timing is encoded into the device’s PCI bus status register. If
no agent asserts PCI_DEVSEL within three clock cycles of PCI_FRAME, the agent responsible for
subtractive decoding may claim the transaction by asserting PCI_DEVSEL.
16-48
Device Selection
I/O Space Addressing
Configuration Space Addressing
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
10
11
Table 16-48. Supported Combinations of PCI_AD[1:0] (continued)
Section 16.4.2.8.2, “Target-Initiated Termination,”
PCI_AD[1:0]
Cache Wrap
Reserved
Read
for descriptions of the two formats.
TD
Target
Write
TD
TD
Read
—
—
Initiator
for more information.
Write
—
—
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