MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 245

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 6-24
Table 6-21
Figure 6-25
Table 6-22
6.4
Data from an I/O master can be allocated into the L2 cache while simultaneously being written to memory.
External (stashed) writes can be performed from any I/O master. For example:
Freescale Semiconductor
Offset 0x2_0E54
Offset 0x2_0E58
16–23
24–31
Reset
Reset
8–15
Bits
0–7
•
•
•
W
W
R
R
Ethernet
PCI/PCI-Express
DMA
0
0
28–31
0–27
Bits
L2CTHRESH L2 cache threshold. Threshold value for the number of ECC single-bit errors that are detected before
L2CCOUNT L2 count. Counts ECC single-bit errors detected. If L2CCOUNT equals the ECC single-bit error
External Writes to the L2 Cache (Cache Stashing)
describes L2ERRADDRH[L2ADDRH].
describes L2ERRCTL fields.
shows the L2 error address capture register high (L2ERRADDRH).
shows the L2 error control register (L2ERRCTL).
Name
—
—
—
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Figure 6-24. L2 Error Address Capture Register (L2ERRADDRH)
L2ADDRH
Reserved
reporting an error condition.
Reserved
trigger threshold, an error is reported if single-bit error reporting is enabled.
Name
—
Figure 6-25. L2 Error Control Register (L2ERRCTL)
7
Table 6-21. L2ERRADDRH Field Description
Table 6-22. L2ERRCTL Field Descriptions
8
Reserved
L2 address bits 0–3 corresponding to detected error
L2CTHRESH
—
All zeros
All zeros
15 16
Description
Description
—
23 24
L2 Look-Aside Cache/SRAM
L2CCOUNT
Access: Read/Write
Access: Read Only
27 28
L2ADDRH
6-25
31
31